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1 features ? aal1 segmentation and reassembly device compatible with structured data transfer (sdt) as per ansi t1.630 and itu i.363 standards ? transports 64kbps and n x 64kbps traf?c over atm aal1 cells (also over aal5 or aal0) ? simultaneous processing of up to 1024 bidirectional virtual circuits ? flexible aggregation capabilities (nx64) to allow any combination of 64 kbps channels while maintaining frame integrity (ds0 grooming) ? support for clock recovery - adaptive clock recovery, synchronous residual time stamp (srts), or external ? primary utopia port (level 1, 25 mhz) for connection to external phy devices with data throughput of up to 155 mbps ? secondary utopia port for connection to an external aal5 sar processor, or for chaining multiple mt90500 devices ? 16-bit microprocessor port, con?gurable to motorola or intel timing ? tdm bus provides 16 bidirectional serial tdm streams at 2.048, 4.096, or 8.192 mbps for up to 2048 tdm 64 kbps channels ? compatible with st-bus, mvip, h-mvip and scsa interfaces ? supports master and slave tdm bus clock operation ? loopback function at tdm bus interface ? local tdm bus provides clocks, input pin and output pin for 2.048 mbps operation ? master clock rate up to 60 mhz ? dual rails (3.3v for power minimization, 5v for standard i/o) ? ieee1149 (jtag) interface figure a - mt90500 block diagram external memory controller microprocessor interface tdm clock logic tdm bus interface tx aal1 sar boundary scan tx utopia mux rx utopia vc lookup tables tx / rx external synchronous sram clock signals tdm bus local tdm bus rx aal1 sar jtag interface 16-bit microprocessor address main utopia interface secondary utopia interface to/from from utopia module internal tdm frame buffer registers tdm module 16 lines 2048 x 64 kbps (max.) 32 x 64 kbps out control structures and circular buffers and data buses external external phy atm sar 32 x 64 kbps in clock recovery ds5171 issue 4 april 1999 mt90500 multi-channel atm aal1 sar ordering information MT90500AL 240 pin plastic qfp -40 to +85 c
mt90500 2 applications ? b-isdn (broadband isdn) systems requiring ?exible n x 64kbps transport ? connecting tdm backplane to tdm backplane over atm network (go-mvip mc4, or other) ? systems requiring ansi t1.630 structured data transfer services for 1 to 122 tdm channels per vc ? systems requiring itu-t i.363.1 circuit transport over structured data transfer for 1 to 96 tdm channels per vc ? systems requiring af-vtoa-0078.000 (atm forum ces v2.0) logical nx64 basic service ? systems requiring af-vtoa-0083.000 voice and telephony over atm (cbr-aal5). ? mapping between cbr-aal0, cbr-aal5, and aal1 ? mapping between cbr partially-?lled cells and full cells ? mapping between cbr single-voice cells and nx64 cells ? atm uplink for expansion of cos, pbxs, or open switching platforms using an adjunct atm switch ? atm public network access for pbx or co ? atm edge switches and cpe integrated- access over atm ? tdm traf?c transfer over an asynchronous cell bus ? systems requiring nx64 over cbr-aal5. description the mt90500 multi-channel aal1 sar is a highly integrated solution which allows systems based on a telecom bus to be interfaced to atm networks using atm adaptation layer 1 (aal1), atm adaptation layer 5 (aal5) and atm adaptation layer 0 (aal0). the mt90500 can be connected directly to a st-bus time division multiplexed (tdm) backplane containing up to 1024 full duplex 64kbps channels. up to 1024 bi-directional atm vc connections can be simultaneously processed by the mt90500 aal1 sar device. on the synchronous tdm bus side, the mt90500 device interfaces with sixteen bidirectional st-bus serial links operating at 2.048, 4.096 or 8.192 mbps. tdm bus compatibility with mvip-90, h-mvip, and scsa interfaces is also provided. on the atm interface side, the mt90500 device meets the atm forum standard utopia bus level 1. this supports connection to a range of standard physical layer (phy) transceivers. the mt90500 provides a built-in utopia multiplexer which allows external atm cells to be multiplexed with internally-generated cells in the transmit direction. this feature can be used to connect another mt90500 (to expand the tdm bandwidth of the system to 4096 tdm channels), or to connect an external aal5 sar (to multiplex non-cbr atm cell traf?c with the mt90500 cbr stream). figure b - mt90500 device application block diagram mt90500 aal1 sar tdm data, clock and sync lines mvip-90 idl st-bus scsa off-the-shelf sar device (aal5) local memory off-the-shelf atm phy device utopia port external cpu 16-bit cpu port for internal register and external memory pro- gramming h-mvip synchronous sram primary utopia port secondary
mt90500 3 table of contents 1. introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 1.1 functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 1.2 reference documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 1.3 atm glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2. features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.1 general . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.2 serial tdm bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.3 cbr atm cell processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.4 external memory interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.5 utopia interface and multiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.6 microprocessor interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.7 miscellaneous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.8 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.8.1 module level interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.8.2 tx_sar interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.8.3 rx_sar interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.8.4 utopia interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.8.5 tdm interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.8.6 timing module interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.9 statistics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.9.1 rx_sar statistics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.9.2 tdm statistics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.9.3 timing recovery statistics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3. pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4. functional description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 4.1 tdm module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 4.1.1 tdm clock logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 4.1.1.1 tdm timing modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 4.1.1.2 ref8kclk selection logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 4.1.1.3 main tdm bus timing and clock generation logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 4.1.1.4 tdm clock drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 4.1.1.5 clock failure detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 4.1.2 tdm interface operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 4.1.2.1 main tdm bus operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 4.1.2.2 tdm loopback. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 4.1.2.3 per-channel output enable feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 4.1.2.4 local bus operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 4.1.2.5 local bus data transfer process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 4.1.3 tdm data to external memory process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 4.1.3.1 general . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 4.1.3.2 transmit circular buffer control structures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 4.1.3.3 transmit circular buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 4.1.4 external memory to tdm data output process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 4.1.4.1 general . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 4.1.4.2 external memory to internal memory control structures . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 4.2 external memory controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 4.3 tx_sar module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 4.3.1 tx_sar overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 4.3.1.1 general . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 4.3.1.2 supported atm cell formats. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 4.3.1.3 transmit event scheduler overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 4.3.1.3.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 4.3.1.3.2 fixed tdm payload schedulers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 4.3.1.3.3 aal1 long/short schedulers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 4.3.1.3.4 other considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
mt90500 4 4.3.2 tx_sar process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48 4.3.2.1 transmit event schedulers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48 4.3.2.2 transmit control structures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 4.3.3 non-cbr data cell transmission capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 4.4 the rx_sar module. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 4.4.1 rx_sar overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 4.4.2 rx_sar process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 4.4.2.1 rx_sar control structures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58 4.4.2.2 rx_sar error counter and interrupt sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 4.4.2.3 receive overruns and underruns. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 4.4.2.4 lost cell handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 4.5 utopia module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62 4.5.1 utopia overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62 4.5.2 cell transmission and mux process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63 4.5.3 receive cell selection process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63 4.5.4 non-cbr data cell reception ability. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67 4.6 clock recovery from atm link . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70 4.6.1 adaptive clock recovery sub-module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70 4.6.2 srts clock recovery description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72 4.6.2.1 transmit srts operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72 4.6.2.2 receive srts operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74 4.7 microprocessor interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77 4.7.1 general. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77 4.7.2 a programming example - how to set up a vc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77 4.7.3 microprocessor access and device reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78 4.8 test interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78 4.8.1 test access port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78 4.8.2 jtag id . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79 4.8.3 boundary scan instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79 4.8.4 bsdl . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79 5. register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80 5.1 register overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80 5.1.1 general. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80 5.1.2 interrupt structure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81 5.1.3 register summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82 5.2 register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84 5.2.1 microprocessor interface registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84 5.2.2 tx_sar registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87 5.2.3 rx_sar registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91 5.2.4 utopia registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94 5.2.5 tdm interface and clock interface registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98 5.2.6 tdm time slot control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111 6. electrical specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112 6.1 dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112 6.2 ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .114 6.2.1 main tdm bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .114 6.2.2 local tdm bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .120 6.2.3 cpu interface - accessing registers and external memory . . . . . . . . . . . . . . . . . . . . . . . . . . . .124 6.2.4 interface with external memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .128 6.2.5 utopia interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .131 6.2.5.1 primary utopia interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .131 6.2.5.2 secondary utopia interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .133 6.2.6 srts user interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .134 6.2.7 message channel interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .134 6.2.8 boundary-scan test access interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .136 7. applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .137 7.1 board level applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .137
mt90500 5 7.2 system level applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 7.3 tdm clock recovery applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 7.3.1 general . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 7.3.2 srts clock recovery considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 7.3.3 free-running clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 7.4 external memory space and bandwidth calculations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 47 7.4.1 external memory space requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 7.4.2 memory structure summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 7.4.3 external memory bandwidth requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 7.5 cbr throughput delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 7.6 other applications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 7.6.1 payload switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 7.6.2 tdm switching and loopback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 7.6.3 ds0 trunking, or dynamic tdm channel re-mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 7.6.4 scsa message channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 8. physical specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
mt90500 6 list of figures figure 1 - mt90500 block diagram................................................................................................ ...................12 figure 2. pin connections ....................................................................................................... .........................26 figure 3 - tdm clock selection and generation logic ............................................................................. ........29 figure 4 - tdm frame buffer to external memory transfer......................................................................... .....33 figure 5 - transmit circular buffer control structure ........................................................................... .............34 figure 6 - external memory to tdm frame buffer transfer......................................................................... .....35 figure 7 - external memory to internal memory control structure................................................................. ...37 figure 8 - memory read pipeline length.......................................................................................... ................38 figure 9 - logical byte address vs. physical address and memory banks ......................................................39 figure 10 - read / write turnaround cycles...................................................................................... .................40 figure 11 - read / read turnaround cycles....................................................................................... ................41 figure 11 - read / write turnaround cycles ...................................................................................... ..................41 figure 12 - aal1 atm cell format ................................................................................................ .....................42 figure 13 - partially-filled aal1 and cbr-aal0 cell formats..................................................................... ......43 figure 14 - cbr-aal5 cell format ............................................................................................... .....................44 figure 15 - transmit event scheduler............................................................................................ .....................49 figure 17 - transmit control structure format (cbr-aal5)........................................................................ .......50 figure 16 - transmit control structure format (aal1 & cbr-aal0) ................................................................. 51 figure 18 - a: sample three-channel transmit control structure (aal1/cbr-aal0) .......................................53 figure 18 - b: sample one-channel transmit control structure (cbr-aal5) ...................................................53 figure 19 - overview of cbr data transmission process........................................................................... .......54 figure 20 - vc pointer for scheduler-controlled non-cbr data cell ............................................................... 55 figure 21 - transmit non-cbr data cell structure format ......................................................................... .......56 figure 22 - rx_sar control structure............................................................................................ ....................58 figure 23 - overrun and underrun situations ..................................................................................... ................60 figure 24 - mt90500 daisy chain example......................................................................................... ...............62 figure 25 - mux and internal fifo sub-module block diagram ...................................................................... ...63 figure 26 - receive cell selection process ...................................................................................... ..................65 figure 27 - mt90500 cell receive process........................................................................................ ................66 figure 28 - look-up table non-cbr data entry.................................................................................... .............67 figure 29 - received non-cbr data cell internal format.......................................................................... ........68 figure 30 - overview of cbr data reception process.............................................................................. .........69 figure 31 - adaptive clock recovery sub-module (simplified functional block diagram).................................70 figure 32 - timing reference cell processing state machine...................................................................... ......71 figure 33 - transmit srts operation............................................................................................. ....................73 figure 34 - receive srts operation.............................................................................................. ....................74 figure 35 - clock recovery using srts method (hardware) ......................................................................... ...75 figure 36 - clock recovery using srts method (cpu) .............................................................................. ......76 figure 37 - a typical jtag test connection ...................................................................................... ................79 figure 38. mt90500 interrupt structure .......................................................................................... ...................81 figure 39 - nominal tdm bus timing .............................................................................................. .................114 figure 40 - main tdm bus output clocking parameters - positive frame pulse .............................................115 figure 41 - main tdm bus output clocking parameters - negative frame pulse ...........................................115 figure 42 - main tdm bus - serial output timing ................................................................................. ...........116 figure 43 - main tdm bus - 2/4 sampling ......................................................................................... ...............118 figure 44 - main tdm bus - 3/4 sampling ......................................................................................... ...............118 figure 45 - main tdm bus - 4/4 sampling ......................................................................................... ...............119 figure 46 - local tdm bus output parameters - positive frame pulse ...........................................................121
mt90500 7 figure 47 - local tdm bus output parameters - negative frame pulse ........................................................ 121 figure 48 - local tdm bus - positive frame pulse, 2/4 sampling .................................................................. 122 figure 49 - local tdm bus - negative frame pulse, 3/4 sampling................................................................. 1 23 figure 50 - local tdm bus - negative frame pulse, 4/4 sampling................................................................. 1 23 figure 51 - intel cpu interface timing - read access............................................................................ ......... 124 figure 52 - intel cpu interface timing - write access........................................................................... .......... 125 figure 53 - motorola cpu interface timing - read access ......................................................................... .... 126 figure 54 - motorola cpu interface timing - write access........................................................................ ...... 127 figure 55 - external memory interface timing - read cycle ....................................................................... .... 129 figure 56 - external memory interface timing - write cycle...................................................................... ...... 130 figure 57 - primary utopia bus - transmit timing ................................................................................ ........ 131 figure 58 - primary utopia bus - receive timing ................................................................................. ........ 132 figure 59 - secondary utopia interface.......................................................................................... ............... 133 figure 60 - srts user interface timing .......................................................................................... ................ 134 figure 61 - message channel timing .............................................................................................. ................ 135 figure 62 - mt90500 device application block diagram ............................................................................ ..... 137 figure 63 - utopia bus interconnections for two mt90500s and an aal5 sar .......................................... 139 figure 64 - the mt90500 within a lan hub ........................................................................................ ............ 141 figure 65 - using the mt90500 with external sar and atm links in a lan environment............................. 142 figure 66 - access product using internal high speed cell bus on the backplane......................................... 142 figure 67 - tdm traffic transport over a cell bus............................................................................... ........... 143 figure 68 - connecting cti platforms to atm lans................................................................................ ........ 143 figure 69 - the go-mvip, pc-atm bus standard architecture...................................................................... 1 44 figure 70 - srts clocking application ........................................................................................... ................. 146 figure 71 - tdm payload switching ............................................................................................... .................. 154 figure 72 - tdm-to-tdm loopback/switching ....................................................................................... .......... 155 figure 73 - scsa message bus application ....................................................................................... ............ 156
mt90500 8 list of tables table 1 - primary utopia bus pins ............................................................................................... .................19 table 2 - secondary utopia bus pins ............................................................................................. ..............20 table 3 - microprocessor bus interface pins ..................................................................................... ..............20 table 4 - external memory interface pins ........................................................................................ ................21 table 5 - master clock, test, and power pins .................................................................................... .............22 table 6 - tdm port pins......................................................................................................... ..........................23 table 7 - reset state of i/o and output pins.................................................................................... ...............24 table 8 - pinout summary........................................................................................................ ........................25 table 9 - memory size combinations .............................................................................................. ................39 table 10 - effect of psel field on p-byte generation............................................................................ ...........53 table 11 - register summary ..................................................................................................... .......................82 table 12 - main control register ................................................................................................ .......................84 table 13 - main status register................................................................................................. ........................84 table 14 - window to external memory register - cpu ............................................................................. .......85 table 15 - read parity register ................................................................................................. ........................85 table 16 - memory configuration register ........................................................................................ ................86 table 17 - tx_sar control register .............................................................................................. ...................87 table 18 - tx_sar status register............................................................................................... ....................87 table 19 - tx_sar scheduler base register ....................................................................................... ............88 table 20 - tx_sar frame end register ............................................................................................ ...............88 table 21 - tx_sar end ratio register ............................................................................................ .................88 table 22 - tx_sar control structure base address register ....................................................................... ...89 table 23 - transmit data cell fifo base address register ........................................................................ .....89 table 24 - transmit data cell fifo write pointer register ....................................................................... ........89 table 25 - transmit data cell fifo read pointer register........................................................................ .......90 table 26 - rx_sar control register.............................................................................................. ...................91 table 27 - rx_sar status register ............................................................................................... ...................92 table 28 - rx_sar misc. event id register ....................................................................................... ..............92 table 29 - rx_sar misc. event counter register .................................................................................. ..........92 table 30 - rx_sar underrun event id register.................................................................................... ...........93 table 31 - rx_sar underrun event counter register ............................................................................... ......93 table 32 - rx_sar overrun event id register..................................................................................... ............93 table 33 - rx_sar overrun event counter register ................................................................................ .......93 table 34 - utopia control register.............................................................................................. ....................94 table 35 - utopia status register ............................................................................................... ....................94 table 36 - vpi / vci concatenation register..................................................................................... ................95 table 37 - vpi match register ................................................................................................... ........................95 table 38 - vpi mask register .................................................................................................... ........................95 table 39 - vci match register ................................................................................................... ........................95 table 40 - vci mask register .................................................................................................... ........................96 table 41 - vpi timing register .................................................................................................. ........................96 table 42 - vci timing register .................................................................................................. ........................96 table 43 - lookup table base address register................................................................................... ............96 table 44 - receive data cell fifo base address register ......................................................................... .....97 table 45 - receive data cell fifo write pointer register ........................................................................ ........97 table 46 - receive data cell fifo read pointer register......................................................................... .......97 table 47 - tdm interface control register ....................................................................................... .................98 table 48 - tdm interface status register........................................................................................ ..................99
mt90500 9 table 49 - tdm i/o register ..................................................................................................... ...................... 100 table 50 - tdm bus type register................................................................................................ ................. 101 table 51 - local bus type register .............................................................................................. .................. 102 table 52 - tdm bus to local bus transfer register............................................................................... ........ 102 table 53 - local bus to tdm bus transfer register............................................................................... ........ 103 table 54 - tx circular buffer control structure base register................................................................... .... 103 table 55 - external to internal memory control structure base register ....................................................... 103 table 56 - tx circular buffer base address register............................................................................. ........ 104 table 57 - tdm read underrun address register ................................................................................... ...... 104 table 58 - tdm read underrun count register..................................................................................... ........ 104 table 59 - clock module general control register................................................................................ ......... 104 table 60 - clock module general status register ................................................................................. ......... 105 table 61 - master clock generation control register ............................................................................. ....... 106 table 62 - master clock / clkx2 division factor................................................................................. ........... 107 table 63 - timing reference processing control register ......................................................................... .... 107 table 64 - event count register ................................................................................................. .................... 108 table 65 - clkx1 count - low register........................................................................................... ............... 108 table 66 - clkx1 count - high register.......................................................................................... ............... 108 table 67 - divx register ........................................................................................................ ........................ 109 table 68 - divx ratio register .................................................................................................. ..................... 109 table 69 - srts transmit gapping divider register ............................................................................... ...... 109 table 70 - srts transmit byte counter register .................................................................................. ........ 110 table 71 - srts receive gapping divider register ................................................................................ ...... 110 table 72 - srts receive byte counter register ................................................................................... ........ 110 table 73 - output enable registers .............................................................................................. .................. 111 table 74 - absolute maximum ratings ............................................................................................. .............. 112 table 75 - recommended operating conditions ..................................................................................... ....... 112 table 76 - dc characteristics ................................................................................................... ...................... 112 table 77 - main tdm bus output clock parameters ................................................................................. ..... 114 table 78 - main tdm bus data output parameters .................................................................................. ..... 116 table 79 - main tdm bus input clock parameters.................................................................................. ....... 117 table 80 - main tdm bus input data parameters ................................................................................... ....... 117 table 81 - local tdm bus clock parameters ....................................................................................... .......... 120 table 82 - local tdm bus data output parameters................................................................................. ...... 120 table 83 - local tdm bus data input parameters .................................................................................. ....... 122 table 84 - intel microprocessor interface timing - read cycle parameters................................................... 124 table 85 - intel microprocessor interface timing - write cycle parameters................................................... 125 table 86 - motorola microprocessor interface timing - read cycle parameters ........................................... 126 table 87 - motorola microprocessor interface timing - write cycle parameters............................................ 127 table 88 - mclk - master clock input parameters ................................................................................. ....... 128 table 89 - external memory interface timing - clock parameters ................................................................. 1 28 table 90 - external memory interface timing - read cycle parameters........................................................ 128 table 91 - external memory interface timing - write cycle parameters ........................................................ 128 table 92 - primary utopia interface parameters - transmit....................................................................... .. 131 table 93 - primary utopia interface parameters - receive........................................................................ .. 132 table 94 - secondary utopia parameters timing ................................................................................... ..... 133 table 95 - srts interface parameters ............................................................................................ ............... 134 table 96 - message channel parameters........................................................................................... ............ 134 table 97 - boundary-scan test access port timing ................................................................................ ...... 136 table 98 - mt90500 connections to 18-bit synchronous sram.................................................................... 138
mt90500 10 table 99 - mt90500 connections to 32/36-bit synchronous sram................................................................138 table 100 - mt90500 utopia signal directions.................................................................................... ...........140 table 101 - recommended tdm channel numbers for srts vcs .................................................................145 table 102 - limits on cdv on receive srts vc.................................................................................... ..........146 table 103 - summary of external memory structures ............................................................................... ........149
mt90500 11 1. introduction 1.1 functional overview the mitel mt90500 multi-channel aal1 sar bridges a standard isochronous tdm (time division multiplexed) backplane to a standard atm (asynchronous transfer mode) bus. on the tdm bus side, the mt90500 can interface to 16 bidirectional tdm bus links operating at 2.048, 4.096 or 8.192 mbps (compatible with mvip / h- mvip, scsa and mitel st-bus). on the atm interface side, the mt90500 provides the utopia bus standardized by the atm forum. the device provides the aal1 structured data transfer (referred to as sdt from now on in this document) and pointerless structured data transfer mappings de?ned by ansi t1.630- 1993 and itu-t i.363. in addition, the mt90500 provides cbr (constant bit rate) mapping of tdm to aal0, and to aal5 (cbr-aal5). in all data transfer formats, the user simply ports the t1/e1, t3/e3, etc. traf?c onto the tdm backplane before applying it to the mt90500. as well, the device also supports tdm clock recovery using adaptive, srts, or external clock recovery. in the receive direction, atm cells with vcs destined for the mt90500 are extracted from the utopia bus and sent toward the tdm interface. in the transmit direction, the mt90500 provides multiplexing capabilities at the utopia interface to allow the use of an external aal5 sar device, or multiple mt90500 devices. this is useful when cbr data and vbr/abr/ubr data traf?c must be transmitted from the local node on the same physical link. as well, the ability to multiplex internal aal1 cells with external aal5 cells can be used to interleave associated signalling cells and control messages with the aal1 cbr traf?c. the mt90500 also offers some internal support for non-cbr data traf?c. if the application's signalling (non- cbr) data throughput is not high, the mt90500 can transmit and receive aal5 (or other non-cbr data) to / from a pair of fifos. this requires the microprocessor to perform sar functions via software, but may remove the requirement for an external data sar. alternatively, if standard aal5 signalling is not required by the system, the user can use some tdm channels for hdlc or proprietary signalling. segmentation and reassembly of tdm data to / from atm cells is highly ?exible. the mt90500 allows the user to select one or more tdm channels to be carried on an atm logical connection with associated vpi/vci. the number of tdm channels (1 to 122), the vpi/vci, the data transfer method (sdt or pointerless structured data transfer), cell partial-?ll level, and the aal (aal1, cbr-aal5, or cbr-aal0) are all programmable. the time slot assignment circuit has 64 kbps granularity and allows a group of tdm channels to be carried on a single atm logical channel (channel grooming). there is no limitation for distributing n x 64 channels on the tdm bus (i.e. tdm channels on a given vc can be concatenated or dispersed anywhere on the 16 serial data streams). up to 1024 bidirectional virtual circuits (vcs) can be handled simultaneously by the internal aal1 processors. at the maximum tdm rate of 8.192 mbps, up to 2048 input/output 64 kbps channels are available (1024 bidirectional tdm channels). if the atm vcs are carrying multiple tdm channels (n x 64), less vcs will be created. the user is given the ability to ?exibly de?ne which 64 kbps channels will be converted into atm vcs. it should be noted that since the mt90500s serial tdm port is fully bidirectional, the atm logical connections can be de?ned as full duplex channels (e.g. voice conversation) or one-way connections (e.g. video playback). using the full duplex capabilities, up to 1024 simultaneous phone calls could be handled by the mt90500. the mt90500 allows the user to scale the size of the external synchronous memory to suit the application. the external memorys size is in?uenced by the number of virtual circuits required, the number of tdm channels being handled, and the amount of cell delay variation (cdv) tolerance required for the receive vcs. user- de?ned lookup tables, data cell fifos, and multiple event schedulers also in?uence the amount of external memory required. the mt90500 supports two clocking schemes on the tdm bus: clock master and clock slave. in clock master, the mt90500 drives the clocks onto the tdm backplane (the tdm clock is recovered from an incoming atm vc, or from an external source). in clock slave mode, the mt90500 receives its 8 khz framing and clocks (4.096, 8.192 or 16.384 mhz) from the tdm backplane, and times its internal functions from that. figure 1 on page 12 shows the mt90500 block diagram. the applications section of this document illustrates several connectivity options with external phy and sar devices.
mt90500 12 1.2 reference documents mt90500 programmers manual. msan-171 - tdm clock recovery from cbr-over-atm links using the mt90500. itu-t rec. i.363.1, b-isdn atm adaptation layer speci?cation: type 1 aal, 08/1996. ansi t1.630, broadband isdn - atm adaptation layer for constant bit rate services functionality and speci?cation, 1993. af-phy-0017, utopia, an atm-phy interface speci?cation: level 1, version 2.01, march 21, 1994. af-vtoa-0078.000, circuit emulation service interoperability speci?cation, version 2.0, jan. 1997. af-vtoa-0083.000, voice and telephony over atm to the desktop speci?cation, version 2.0, may 1997. m. noorchasm et al. , buffer design for constant bit rate services in presence of cell delay variation, atm forum contribution 95-1454. paul e. fleischer and chi-leung lau, synchronous residual time stamp for timing recovery in a broadband network, united states patent 5,260,978, nov. 1993. ieee std. 1149.1a-1993, ieee standard test access port and boundary scan architecture. figure 1 - mt90500 block diagram tdm bus interface logic tx aal1 sar rx aal1 sar tdm bus 16 lines 2048 x 64kbps (max.) tx utopia mux rx utopia block vc look-up tables tx / rx control structures and circular buffers main utopia interface secondary utopia interface boundary- scan logic from external sar to/from external phy jtag interface 16-bit microprocessor inter- face external memory controller tdm clock logic clock signals external synchronous sram tdm module internal tdm frame buffer microprocessor interface logic registers utopia module local tdm bus 32 x 64 kbps in / 32 x 64 kbps out clock recovery mt90500
mt90500 13 1.3 atm glossary aal - atm adaptation layer ; standardized protocols used to translate higher layer services from multiple applications into the size and format of an atm cell. aal0 - native atm cell transmission; proprietary protocol featuring 5-byte header and 48-byte user payload. aal1 - atm adaptation layer used for the transport of constant bit rate, time-dependent traf?c (e.g. voice, video); requires transfer of timing information between source and destination; maximum of 47-bytes of user data permitted in payload as an additional header byte is required to provide sequencing information. aal5 - atm adaptation layer usually used for the transport of variable bit rate, delay-tolerant data traf?c and signalling which requires little sequencing or error-detection support . ansi t1.630 - american national standards institute speci?cation: broadband isdn - atm adaptation layer for constant bit rate services functionality and speci?cation. asynchronous - 1. not synchronous ; not periodic. 2. the temporal property of being sourced from independent timing references. asynchronous signals have different frequencies, and no ?xed phase relationship. 3. in telecom, data which is not synchronized to the public network clock. 4. the condition or state when an entity is unable to determine, prior to its occurrence, exactly when an event will transpire. atm - asynchronous transfer mod e; a method in which information to be transferred is organized into ?xed- length cells; asynchronous in the sense that the recurrence of cells containing information from an individual user is not necessarily periodic. (while atm cells are transmitted synchronously to maintain clock between sender and receiver, the sender transmits data cells when it has something to send and transmits empty cells when idle, and is not limited to transmitting data every nth cell.) cell - ?xed-size information package consisting of 53 bytes (octets) of data; of these, 5 bytes represent the cell header and 48 bytes carry the user payload and required overhead. cbr - constant bit rate ; an atm service category supporting a constant or guaranteed rate, with timing control and strict performance parameters. used for services such as voice, video, or circuit emulation. cdv - cell delay variation ; a qos parameter that measures the peak-to-peak cell delay through the network; results from buffering and cell scheduling. ces - circuit emulation service ; atm forum service providing a virtual circuit which emulates the characteristics of a constant bit rate, dedicated-bandwidth circuit (e.g. t1). clp - cell loss priority ; a 1-bit ?eld in the atm cell header that corresponds to the loss priority of a cell; cells with clp = 1 can be discarded in a congestion situation. csi - convergence sublayer indication bit in the aal1 header byte; when present in an even-numbered cell using sdt , indicates the presence of a pointer byte; used to transport rts values in odd-numbered cells using srts for clock recovery. gfc - generic flow control ; 4-bit ?eld in the atm header used for local functions (not carried end-to-end); default value is 0000, meaning that gfc protocol is not enforced. hec - header error control ; using the ?fth octet in the atm cell header, atm equipment (usually the phy ) may check for an error and correct the contents of the header; crc algorithm allows for single-error correction and multiple-error detection. i.363 - itu-t recommendation specifying the aals for b-isdn (broadband isdn). isochronous - the temporal property of an event or signal recurring at known periodic time intervals (e.g. 125 m s). isochronous signals are dependent on some uniform timing, or carry their own timing information embedded as part of the signal. examples are ds-1/t1, e1 and tdm in general. from the root words, iso meaning equal, and chronous meaning time. oam bit - operations, administration and maintenance ; msb within the pti ?eld of the atm cell header which indicates if the atm cell carries management information such as fault indications. plesiochronous - the temporal property of being arbitrarily close in frequency to some de?ned precision. plesiochronous signals occur at nominally the same rate, any variation in rate being constrained within speci?c limits. since they are not identical, over the long term they will be skewed from each other. this will force a
mt90500 14 switch to occasionally repeat or delete data in order to handle buffer under?ow or over?ow. (in telecommunications, this is known as a frame slip). phy - physical layer ; bottom layer of the atm reference model; provides atm cell transmission over the physical interfaces that interconnect the various atm devices. pti - payload type identi?er ; 3-bit ?eld in the atm cell header - msb indicates if the cell contains oam information or user data; lsb indicates that a aal5 cell is the ?nal cell in a frame. qos - quality of service ; atm performance parameters that characterize the transmission quality over a given vc (e.g cell delay variation; cell transfer delay, cell loss ratio). rts - residual time stamp ; see srts. sar - segmentation and reassembly ; method of partitioning, at the source, frames into atm cells and reassembling, at the destination, these cells back into information frames; lower sublayer of the aal which inserts data from the information frames into cells and then adds the required header, trailer, and/or padding bytes to create 48-byte payloads to be transmitted to the atm layer. sdt - structured data transfer ; format used within aal1 for blocks consisting of n * 64 kbps channels; blocks are segmented into cells for transfer and additional overhead bytes (pointers) are used to indicate structure boundaries within cells (therefore aiding clock recovery). sn - sequence number ; 4-bit ?eld in the aal1 header byte used as a sequence counter for detecting lost or misinserted atm cells. snp - sequence number protection ; 4-bit ?eld in the aal1 header byte consisting of a crc and a parity bit which are designed to provide error-correction on the sn. srts - synchronous residual time stamp; method for clock recovery in which difference signals between a source clock and the network reference clock (time stamps) are transmitted to allow reconstruction of the source clock. the destination reconstructs the source clock based on the time stamps and the network reference clock. (note that the same network reference clock is required at both ends.) ssram - synchronous static ram. synchronous - 1. the temporal property of being sourced from the same timing reference. synchronous signals have the same frequency, and a ?xed (often implied to be zero) phase offset. 2. a mode of transmission in which the sending and receiving terminal equipment are operating continually at the same rate and are maintained in a desired phase relationship by an appropriate means. udt - unstructured data transfer ; format used within aal1 for transmission of user data without regard for structure boundaries (e.g. circuit emulation); term used within ansi standard - not explicitly stated in itu. utopia - universal test and operations physical interface for atm; a phy -level interface to provide connectivity between atm components. vc - virtual channel; one of several logical connections de?ned within a virtual path ( vp ) between two atm devices; provides sequential, unidirectional transport of atm cells. also virtual circuit. vci - virtual channel identi?er; 16-bit value in the atm cell header that provides a unique identi?er for the virtual channel ( vc ) within a virtual path ( vp ) that carries a particular cell. vp - virtual path; a unidirectional logical connection between two atm devices; consists of a set of virtual channels ( vc ). vpi - virtual path identi?er; 8-bit value in the atm cell header that indicates the virtual path ( vp ) to which a cell belongs. vtoa - voice and telephony over atm; intended to provide voice connectivity to the desktop, and to provide interoperability with existing n-isdn and pbx services. glossar y ref erences: the atm glossary - atm year 97 - version 2.1, march 1997 the atm forum glossary - may 1997 atm and networking glossary (http://www.techguide.com/comm/index.html) mitel semiconductor glossary of telecommunications terms - may 1995.
mt90500 15 2. features 2.1 general the mt90500 device external interfaces are: ? tdm (time division multiplexed) bus composed of 16 serial streams running at up to 8.192 mbps, plus related clocks and control signals, con?gurable by software. this interface also includes vari- ous signals for tdm clock signal generation. this bus carries telecom or other data in n x 64 kbps streams. ? local serial tdm bus interface (a tdm input pin, a tdm output pin, and clocks). ? a primary utopia bus running at up to 25 mhz, suitable for connection to a 25 mbps or 155 mbps phy device. ? a secondary utopia bus, for connection of an optional external sar (e.g. data) device running at up to 25 mhz. in this case, the mt90500 device emulates a phy device for the external sar. ? a synchronous 36-bit wide memory interface running at up to 60 mhz. ? a 16-bit microprocessor interface used for device con?guration, status, and control. ? signals for general clocking, reset, and jtag boundary-scan. 2.2 serial tdm bus ? compatible with st-bus, mvip, h-mvip, idl, and scsa interfaces. ? provides 16 bidirectional serial streams that can operate at tdm data rates of 2.048, 4.096 or 8.192 mbps for up to 2048 tdm 64 kbps channels (1024 bidirectional ds0 channels: supports 32 e1 framers, or 42 t1 framers, or 10 j2 framers). ? serial tdm bus clocking schemes: tdm timing bus slave (mt90500 slaved to tdm bus), tdm tim- ing bus master (mt90500 drives clocks onto tdm bus - freerun, or synchronized to 8 khz refer- ence) and tdm bus master-alternate (mt90500 slaved to tdm bus, but ready to switch to 8 khz reference). ? additional local tdm bus interface (2.048 mbps) allows local tdm devices to access the main tdm bus. 2.3 cbr atm cell processor ? independent segmentation and reassembly blocks for receive and transmit (rx_sar and tx_sar) support cbr (constant bit rate) transport of half- or full-duplex tdm channels. ? compatible with structured data transfer (sdt) services as per ansi t1.630 standard for 1 to 122 tdm channels per vc. ? compatible with itu-t i.363.1 circuit transport of 8 khz structured data using structured data transfer (sdt) for 1 to 96 tdm channels per vc (using buffer-?ll level monitoring). ? compatible with itu-t i.363.1 voiceband signal transport. ? compatible with af-vtoa-0078.000 n x 64 basic service (non-cas) circuit emulation (using buffer-level monitoring, rather than lost cell insertion). ? compatible with af-vtoa-0078.000 for sdt of partially-?lled aal1 cells with n-channel struc- tures (where n does not exceed the value of the partial-?ll). ? aal1 sar-pdu header processing (aal1 sequence number checking). ? supports up to 1024 bidirectional vcs (virtual circuits) simultaneously. ? supports up to 1024 transmit tdm channels and 1024 receive tdm channels simultaneously. ? supports cbr-aal0 (48 byte cell payload). ? supports cbr-aal5 as per af-vtoa-0083.000, also supports nx64 trunking over cbr-aal5.
mt90500 16 ? supports partially-?lled cells (aal1, cbr-aal5, and cbr-aal0). ? user-de?ned, per-vc, cell delay variation tolerance: 8 to 128 ms buffer size (up to 64 ms cdv). ? handles tdm channels at 64 kbps granularity. ? each individual vc can be composed of n x 64 kbps wideband channels (n = 1, 2, ..., 122). ? flexible aggregation capability (n x 64 kbps) maintains frame integrity, while allowing any combi- nation of 64 kbps channels (ds0 grooming). ? supports multi-casting of one tdm ds0 input channel to multiple transmit atm vcs, and of one receive atm ds0 to multiple tdm outputs. ? a vc can contain any combination of tdm channels from any combination of tdm streams (nx64) and maintain frame integrity for those channels. ? supports several 8 khz synchronisation operations: synchronized to external 8 khz reference, synchronized to network clock, and synchronized to timing derived from an atm vc (including itu-t i.363.1 adaptive and srts clock recovery mechanisms). 2.4 external memory interface ? to implement sar functions and buffers, the mt90500 device uses external synchronous sram. ? external synchronous sram size is chosen by user, and depends on cell delay variation (cdv) and the number of simultaneous 64 kbps channels handled. the amount of synchronous sram is scalable to suit the application, and may range from 128 kbytes to 2,048 kbytes. 2.5 utopia interface and multiplexer ? utopia level 1 compatible 8-bit bus, running at up to 25 mbyte/s, for connection to phy devices with data throughput of up to 155 mbps. ? transmit multiplexer mixes cells from tx_sar and secondary utopia port, supporting another mt90500, and/or an external sar device (e.g. aal5) connected to a single phy device. ? programmable multiplexer priority gives internally generated aal1 cells equal, or higher, priority than cells coming from secondary utopia port. ? supports non-cbr data cells and oam cells destined for microprocessor with receive and trans- mit data cell fifos. ? flexible receive cell handling: aal1 (as well as cbr-aal0 and cbr-aal5) cells are sent to the tdm port; data cells (non-cbr data and oam cells) are sent to the receive data cell fifo; cells with unrecognized vcs may be queued or ignored. ? cell reception based on look-up-table allows ?exible vc assignment for cbr vcs (allows non- contiguous vc assignment). ? programmable vpi/vci match and mask ?ltering reduces unnecessary look-up-table accesses. 2.6 microprocessor interface ? 16-bit microprocessor port, con?gurable to motorola or intel timing. ? programmable interrupts for control and statistics. ? allows access to internal registers for initialization, control, and statistics. ? allows access to external ssram for initialization, control, and observation. 2.7 miscellaneous ? master clock rate up to 60 mhz. ? dual rails (3.3v for power minimization, 5v for standard i/o). ? loopback function provided at the tdm interface.
mt90500 17 ? ieee 1149 (jtag) boundary-scan test access port for testing board-level interconnect. ? packaging: 240-pin pqfp. 2.8 interrupts the mt90500 provides a wide variety of interrupt source bits, allowing for easy monitoring of mt90500 operation. all interrupt source bits, including the module level interrupt bits, have an associated mask bit which enables or disables assertion of the interrupt pin. this enables the user to tailor the interrupt pin activity to the application. interrupt source bits are set regardless of the state of the associated mask bit, so even source bits which are disabled from causing an interrupt pin assertion may be polled by the cpu by reading the appropriate register. 2.8.1 module level interrupts the following interrupt bits are used to indicate which mt90500 circuit module is the source of the interrupt. they are set when one or more interrupt source bits in the particular circuit module is set. the cpu can ?nd the source of an interrupt by reading the register containing these bits and then reading the indicated modules interrupt register. ? tx_sar module interrupt ? rx_sar module interrupt ? utopia module interrupt ? tdm module interrupt ? timing (tdm clock generation) module interrupt 2.8.2 tx_sar interrupts ? transmit non-cbr data cell fifo overrun interrupt ? scheduler error (indicates that the tx_sar has too heavy a work load.) 2.8.3 rx_sar interrupts ? aal1-byte parity error interrupt ? aal1-byte crc error interrupt ? aal1-byte sequence number error interrupt ? pointer-byte parity error interrupt ? pointer-byte out of range error interrupt ? underrun error interrupt ? overrun error interrupt ? miscellaneous counter rollover interrupt ? underrun counter rollover interrupt ? overrun counter rollover interrupt 2.8.4 utopia interrupts ? receive non-cbr data cell fifo overrun interrupt ? rx utopia module internal fifo overrun interrupt ? receive non-cbr data cell fifo receive cell interrupt 2.8.5 tdm interrupts ? clock absent interrupt ? clock fail interrupt ? tdm out of bandwidth interrupt
mt90500 18 ? tdm read underrun error interrupt ? tdm read underrun counter rollover interrupt 2.8.6 timing module interrupts ? 8 khz reference failure interrupt ? srts tx underrun interrupt ? srts tx overrun interrupt ? srts rx underrun interrupt ? srts rx overrun interrupt ? adaptive clock loss of timing reference cell interrupt ? adaptive clock loss of synchronization interrupt 2.9 statistics the mt90500 provides a number of statistics to allow monitoring of the mt90500. these statistics generally parallel the operation of some of the interrupt source bits. the counters (except the timing recovery counters) also set rollover interrupt source bits when they reach their terminal counts and return to zero. 2.9.1 rx_sar statistics ? miscellaneous event counter: this 16-bit registers value is incremented each time a (mask- selected) miscellaneous error occurs. ? aal1-byte parity error ? aal1-byte crc error ? aal1 sequence number error ? pointer-byte parity error ? pointer-byte out of range error ? miscellaneous event id register: the address of the rx control structure that caused the last miscellaneous error. ? underrun count: this 16-bit registers value is incremented each time a cbr receive underrun occurs. ? underrun id number: the address of the rx control structure that caused the last underrun error. ? overrun count: this 16-bit register is incremented each time a cbr receive overrun occurs. ? overrun id number: the address of the rx control structure that caused the last overrun error. 2.9.2 tdm statistics ? tdm read underrun time slot stream. contains the time slot and stream on which the last tdm read underrun was detected. ? tdm read underrun counter. each time a tdm read underrun occurs, this registers value is incremented. 2.9.3 timing recovery statistics ? event counter: counts the reception of timing reference cells or 8 khz markers. ? clkx1 counter: 24-bit counter which keeps a running count of tdm byte-periods.
mt90500 19 3. pin descriptions i/o types are: output (o), input (i), bidirectional (i/o), power (pwr), or ground (gnd). input pad types are: ttl, cmos, differential, or schmitt. the notations pu and pd are used, respectively, to indicate that a pad has an internal pullup or pulldown resistor. ttl (5v) inputs are pulled-up to the 5v rail, cmos (3.3v) inputs are pulled-up to the 3.3v rail. these weak internal resistors should not be relied upon for fast data transitions. the 3.3v cmos inputs have a switching threshold of 1.6v, and tolerate input levels of up to 5v; therefore they are 5v ttl compatible (with the exception of the trist a te pin, which is not 5v tolerant). output pad types are generally described by voltage and current capability. output types used are: 3.3v, 4ma; 5v, 4ma; 5v, 12ma; and open-drain. a notation of sr indicates that the pad is slew-rate limited. 3.3v cmos outputs will satisfy 5v ttl input thresholds at the rated current. table 1 - primary utopia bus pins pin # pin name i/o type description 49, 48, 47, 46, 45, 44, 39, 38 ptxdata[7:0] o 5v, 4ma primary utopia transmit data bus. byte-wide data driven from mt90500 to phy device. bit 7 is the msb. 52 ptxsoc o 5v, 4ma primary utopia transmit start of cell signal. asserted by the mt90500 when ptxdata[7:0] contains the first valid byte of the cell. 51 ptxen o 5v, 4ma primary utopia transmit data enable. active low signal asserted by the mt90500 during cycles when ptxdata[7:0] contains valid cell data. 53 ptxclav i ttl pu primary utopia transmit cell available indication signal. for cell level flow control, ptxclav is asserted by the phy to indicate to the mt90500 that the phy can accept the transfer of a complete cell. 82 ptxclk i/o ttl pu / 5v, 4ma sr primary utopia transmit clock. data transfer & synchronization clock provided by the mt90500 to the phy for transmitting data on ptxdata[7:0]; software configurable (in main control register at 0000h) to run at up to 25 mhz. note that this pin should be configured as an output for exact compliance with utopia level 1, v2.01. 50 ptxpar o 5v, 4ma primary utopia transmit parity. this signal is the odd parity bit over ptxdata[7:0]. 57, 58, 59, 62, 63, 64, 65, 66 prxdata[7:0] i ttl pu primary utopia receive data bus. byte-wide data driven from the phy to the mt90500. prxdata[7] is the msb. 56 prxsoc i ttl pu primary utopia receive start of cell signal. asserted by the phy when prxdata[7:0] contains the first valid byte of a cell. 55 prxen i ttl pu primary utopia bus data enable. active low signal normally asserted by the secondary sar to indicate that prxdata[7:0], prxsoc, and prxclav will be sampled at the end of the next clock cycle. if no secondary sar is used, ground this pin at the mt90500 and phy devices. note that the utopia standard permits this signal to be permanently asserted (see utopia level 1, v2.01, footnote 6). 54 prxclav i ttl pu primary utopia receive cell available indication signal. for cell level flow control, prxclav is asserted by the phy to indicate it has a complete cell available for transfer to the rx utopia port. 79 prxclk i ttl pu primary utopia bus receive clock. this clock, which can run at up to 25 mhz, is provided by the secondary sar device. if no secondary sar is used, connect to ptxclk (this will provide exact compliance with the utopia level 1, v2.01 specification). refer to figure 63 on page 139 for implementation details regarding the interface between two mt90500s and an external aal5 sar.
mt90500 20 table 2 - secondary utopia bus pins pin # pin name i/o type description 70, 71, 72, 73, 74, 75, 76, 77 stxdata[7:0] i ttl pu secondary utopia transmit data bus. byte-wide data driven from the external sar to the mt90500. bit 7 is the msb. 69 stxsoc i ttl pu secondary utopia transmit start of cell signal. asserted by the external sar device when stxdata[7:0] contains the first valid byte of the cell. 68 stxen i ttl pu secondary utopia transmit data enable. active low signal asserted by the external sar during cycles when stxdata[7:0] contains valid cell data. 67 stxclav o 5v, 4ma secondary utopia transmit cell available indication signal. for cell level flow control, stxclav is asserted by the mt90500 to indicate to the external sar that the mt90500 can accept the transfer of a complete cell. 85 stxclk i ttl pu secondary utopia transmit clock, which can run at up to 25 mhz. data transfer & synchronization clock provided by the external sar to the mt90500 for transmitting data over stxdata[7:0]. note: mt90500 secondary utopia port emulates a phy device for connection to an external sar (atm-layer device). refer to figure 63 on page 139 for implementation details regarding the interface between the mt90500 and an external aal5 sar. table 3 - microprocessor bus interface pins pin # pin name i/o type description 37 intel/ motorola i ttl pu intel interface (1) / motorola interface (0) 36 ic i ttl pu internal connection (must be high). 203 cs i ttl pu active low chip select signal. 237 wr/r\ w i ttl pu active low write strobe (intel) / read- write (motorola). 239 rd/ ds i ttl pu active low read strobe (intel) / active low data strobe (motorola). 238 rdy/ dtack o 5v, 4ma ready (intel) / data transfer acknowledge (motorola). acts as active low pseudo-open-drain in motorola mode ( dtack, see figure 53 on page 126). acts as normal output in intel mode, high impedance when cs is high (rdy). 84 int o 5v, 4ma sr (open-drain) active low interrupt line. 223, 222, 219, 218, 217, 216, 215, 214, 212, 211, 210, 209, 208, 206, 205, 204 d[15:0] i/o ttl pu / 5v, 4ma sr cpu data bus. 184 aem i ttl pu access external memory - cpu accesses external memory when high (internal memory and registers when low). 185, 186, 187, 188, 189, 190, 191, 192, 193, 194, 195, 196, 198, 199, 202 a[15:1] i ttl pu cpu address lines a15-a1. all microprocessor accesses to the device are word-wide, but addresses in this document are given as byte-addresses. the virtual a[0] bit selects between high and low bytes in a word. note: mt90500 ttl inputs are pulled up to the 5 volt rail. see table 76 on page 112.
mt90500 21 table 4 - external memory interface pins pin # pin name i/o type description 98 memclk o 3.3v, 4ma memory clock. internally connected to mclk. 147 mem_cs0l o 3.3v, 4ma active low memory chip select signal. this chip select is used in all memory modes. when there are two chips per bank, mem_cs0l is associated with mem_dat[15:0] of bank 0. 176 mem_cs0h o 3.3v, 4ma active low memory chip select signal. this chip select is used when there are two 16-bit memory chips per bank. mem_cs0h is associated with mem_dat[31:16] of bank 0. 148 mem_cs1l o 3.3v, 4ma active low memory chip select signal. this chip select is used when there are two banks and two chips per bank. mem_cs1l is associated with mem_dat[15:0] of bank 1. 177 mem_cs1h o 3.3v, 4ma active low memory chip select signal. this chip select is used when there are two banks and two chips per bank. mem_cs1h is associated with mem_dat[31:16] of bank 1. 178, 179, 149, 150 mem_wr[3:0] o 3.3v, 4ma active low byte-write enables. mem_wr[3] is associated with mem_dat[31:24]; mem_wr[2] is associated with mem_dat[23:16]; mem_wr[1] is associated with mem_dat[15:8]; mem_wr[0] is associated with mem_dat[7:0]. 180 mem_oe o 3.3v, 4ma active low output enable. 123, 122, 121, 118, 117, 116, 115, 103, 102, 99, 146, 144, 130, 128, 127, 126, 125, 124 mem_add[17:0] o 3.3v, 4ma memory address lines. 166, 167, 168, 170, 171, 173, 174, 175, 153, 154, 155, 156, 158, 159, 162, 164, 133, 134, 135, 136, 137, 138, 142, 143, 105, 106, 107, 108, 109, 112, 113, 114 mem_dat[31:0] i/o 3.3v cmos pu / 3.3v 4ma memory data lines. mem_dat[31:24] represent the upper byte; mem_dat[23:16] represent the upper-middle byte; mem_dat[15:8] represent the lower-middle byte; mem_dat[7:0] represent the lower byte. 165, 152, 131, 104 mem_par[3:0] i/o 3.3v cmos pu / 3.3v 4ma memory parity lines. mem_par[3:0] are the optional parity bits that allow tdm read underrun detection. mem_par[3] is related to mem_dat[31:24], mem_par[2] is related to mem_dat[23:16], mem_par[1] is related to mem_dat[15:8], and mem_par[0] is related to mem_dat[7:0]. when unused, these pins must be pulled up via external resistors. note: mt90500 3.3 v cmos inputs are pulled up to the 3.3 volt rail. see table 76 on page 112.
mt90500 22 table 5 - master clock, test, and power pins pin # pin name i/o type description 87 mclk i ttl pu master clock. this signal drives the internal logic (including the rx_sar and the tx_sar) and the external memory (through memclk). 60 mhz for most applications. mclk should be more than 5 times clkx1, and should be more than 3 times fnxi. 78 reset i 5v ttl schmitt pu chip reset signal (active low). note that the mt90500 is synchronously reset, and that mclk should be applied during reset. to asynchronously tristate outputs, assert the tristate pin. the trst pin (jtag reset) should also be asserted low during chip reset. reset should last at least 2 m s when mclk is 60 mhz. also see sres bit in register 0000h. 97 tms i 3.3v cmos pu jtag test mode select signal. 93 tck i 3.3v cmos pu jtag test clock. 95 tdi i 3.3v cmos pu jtag test data in. 96 tdo o 3.3v, 4ma sr jtag test data out. note: tdo is tristated by tristate pin. 94 trst i 3.3v cmos pd jtag test reset input (active low). should be asserted low on power-up and during reset. must be high for jtag boundary-scan operation. note: this pin has an internal pull-down . 1, 7, 16, 29, 43, 61, 86, 91, 110, 119, 129, 139, 151, 163, 172, 182, 197, 213, 229 io_vss gnd ground for i/o logic. 100, 141, 161 core_vss gnd ground for core logic. 20, 40, 80, 201, 221 ring_vss gnd ground for core logic. 92, 111, 120, 132, 145, 157, 169, 181 io_vdd_3v pwr power for i/o logic (3.3 v). 2, 13, 24, 42, 60, 88, 183, 207, 225, 240 io_vdd_5v pwr power for i/o logic (5 v). 101, 140, 160 core_vdd_3v pwr power for core logic (3.3 v). 21, 41, 81, 200, 220 ring_vdd_3v pwr power for core logic (3.3 v). 89 ic i ic test, must be grounded. 90 tristate i 3.3v cmos pu 3.3v only output tristate control. asynchronously tristates all output pins when low. can be asserted low on power-up and during reset. pull up to 3.3v for normal operation. not 5v tolerant.
mt90500 23 table 6 - tdm port pins pin # pin name i/o type description 25, 23, 22, 19, 18, 17, 15, 14, 12, 11, 10, 9, 8, 6, 5, 4 st[15:0] i/o ttl pu / 5v, 12ma sr tdm data streams. used to pass pcm (voice) bytes or other data types. in order to enable any of these pins as outputs, the genoe bit in the tdm interface control register (6000h) must be set, as well as the appropriate channel bits in the output enable registers. 230 clkx2pi i diff + differential clock signal input (+) running at twice the serial tdm data stream frequency. this pin is used only in differential clock mode (h-mvip) and should be tied high when not in use. for normal (non-differential) clock mode input, use clkx2/clx2po pin. 227 clkx2ni i diff - differential clock signal input (-) running at twice the serial tdm data stream frequency. this pin is used only in differential clock mode (h-mvip) and should be grounded when not in use. 233 clkx1 i/o ttl pu / 5v, 12ma sr clockx1. this signal represents the clkx2 signal divided by 2. 232 fsync i/o ttl pu / 5v, 12ma sr frame sync. bidirectional 8 khz reference to/from main tdm bus. 30 ic i ttl pu internal connection (must be high). 32 corsiga / clkfail i/o ttl pu / 5v, 12ma sr corsiga i/o when not used by the tdm bus. clock fail on scsa bus. 235 corsigb / mc / fnxi i/o ttl pu / 5v, 12ma sr corsigb i/o when not used by the tdm bus. message channel (i/o) on the scsa bus. srts fnx network clock input - this input line is required when srts clock recovery mode is used. note: when used for clock recovery, this clock must be < mclk / 3. 33 corsigc / mctx / srtsena i/o ttl pu / 5v, 4ma sr corsigc i/o when not used by the tdm bus. message channel transmit (input) toward scsa bus from hdlc controller. this signal represents srts ena output when srts clock recovery mode is selected. 34 corsigd / mcrx / srtsdata i/o ttl pu / 5v, 4ma sr corsigd i/o when not used by the tdm bus. message channel receive (output) from scsa bus toward hdlc controller. this signal represents srts data output serial line when srts clock recovery mode is selected. 35 corsige / mcclk i/o ttl pu / 5v, 4ma sr corsige i/o when not used by the tdm bus. message channel hdlc controller clock (output) from the scsa bus. 83 ex_8ka i ttl pu an 8 khz clock input that can be used as reference in the generation of the ref8kclk or sec8k lines. 234 sec8k i/o ttl pu / 5v, 12ma secondary alternate 8 khz clock. compatible with mvip and h-mvip modes. 226 ref8kclk o 5v, 12ma sr an 8 khz clock generated internally. this signal is generated from one of several internal sources which are programmed by the user. this output can provide a reference clock to an external pll to generate the 16.384 / 32.768 mhz required for the operation of the ic in master mode. 224 pllclk i ttl pu 16.384 / 32.768 mhz tdm clock reference from external pll. 31 freerun o 5v, 12ma sr active high external pll freerun indication. 236 locx2 o 5v, 4ma sr local tdm bus clockx2. 3 locx1 o 5v, 4ma sr local tdm bus clockx1. 28 lsync o 5v, 4ma sr local tdm bus frame sync. 26 locsto o 5v, 4ma sr local tdm bus serial data out stream. 27 locsti i ttl pu local tdm bus serial data in stream. 231 clkx2/ clkx2po i/o ttl pu / 5v, 12ma clkx2 input/output / clkx2 positive output. normal (non-differential) clkx2 input in tdm clock slave mode. clkx2 output (differential and non- differential) in tdm clock master mode. 228 clkx2no o 5v, 12ma clkx2 negative output. differential negative output clock. (inverse of clkx2po). used in tdm clock master, differential clock mode (h-mvip); active whenever mt90500 is tdm clock master. (leave unconnected if non-differential clock desired.)
mt90500 24 table 7 - reset state of i/o and output pins pin name i/o reset state additional control information ptxdata[7:0] o active during and after reset. n / a ptxpar o active during and after reset. n / a ptxclk i/o high-impedance the ptxclk_sel bits in the main control register (0000h) are low after reset; ptxclk is tristated and an input. ptxen o active during and after reset. n / a ptxsoc o active during and after reset. n / a stxclav o active during and after reset. n / a memclk o continues to drive at mclk rate during reset. n / a mem_cs[1:0][h:l] o active during and after reset. n / a mem_wr[3:0] o active during and after reset. n / a mem_oe o active high during reset. reset low forces this pin high. after reset, this pin goes low. mem_add[17:0] o active during and after reset. n / a mem_dat[31:0] i/o high-impedance n / a mem_par[3:0] i/o high-impedance n / a rdy/ dtack o active during and after reset. tristated when cs is high. in motorola mode, pin drives high during reset. in intel mode, drives low during reset. int o high-impedance the interrupt enable bits in the main control register at 0000h are reset to zero; interrupts are masked after reset. d[15:0] i/o high-impedance n / a tdo o determined by trst and / or tap controller state n / a st[15:0] i/o high-impedance the genoe bit in the tdm interface control register (6000h) is low after reset; these tdm data pins are tristated and in loopback mode. clkx1 i/o input the clkmaster bit in the tdm bus type register (6010h) resets to 0; the mt90500 is tdm slave, and clkx1 is input from the tdm bus. fsync i/o input the clkmaster bit in the tdm bus type register (6010h) resets to 0; the mt90500 is tdm slave and fsync is input from the tdm bus. corsiga/ clkfail i/o input the tdm i/o register at 6004h resets to all zeroes; all corsigxcnf are set to 00 and all corsigx pins are configured as inputs. corsigb / mc / fnxi i/o input see corsiga. corsigc / mctx / srtsena i/o input see corsiga. corsigd / mcrx / srtsdata i/o input see corsiga. corsige / mcclk i/o input see corsiga. sec8k i/o input the sec8ken bit in the master clock generation control register (6090h) resets to 0; sec8k is an input. ref8kclk o active during and after reset. due to the reset values of the master clock generation control register (6090h) and the master clock / clkx2 division factor (6092h), ref8kclk is initially equal to mclk / 8194. freerun o active high during and after reset. the freerun bits in the master clock generation control register at 6090h are 00 after reset; the freerun pin is reset to active high. locx2 o active during and after reset. n / a locx1 o active during and after reset. n / a
mt90500 25 lsync o active during and after reset. n / a locsto o active during and after reset. n / a clkx2/clkx2po i/o input the clkmaster bit in the tdm bus type register (6010h) resets to 0; the mt90500 is tdm slave and clkx2 is input from the tdm bus. clkx2no o high-impedance the clkmaster bit in the tdm bus type register (6010h) resets to 0; the mt90500 is tdm slave and therefore no clock signals are driven from the mt90500. note: all pins are placed in high-impedance by asserting the tristate pin. table 8 - pinout summary type input output i/o power ground primary utopia 13 11 1 secondary utopia 11 1 external memory interface 28 36 microprocessor interface 21 2 16 miscellaneous 8 1 tdm interface 6 7 25 power 26 ground 27 total 187 + 26 + 27 = 240 59 50 78 26 27 table 7 - reset state of i/o and output pins pin name i/o reset state additional control information
mt90500 26 figure 2. pin connections 240 pin pqfp 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 22 24 26 28 30 182 200 198 196 194 192 188 186 184 190 20 18 16 14 12 10 8 6 4 2 202 220 218 216 214 212 208 206 204 210 222 240 238 236 234 232 228 226 224 230 io_vss io_vdd_5v locx1 st0 st1 st2 io_vss st3 st4 st5 st6 st7 io_vdd_5v st8 st9 io_vss st10 st11 st12 ring_vss ring_vdd_3v st13 st14 io_vdd_5v st15 locsto locsti lsync io_vss ic io_vdd_5v rd/ ds rdy/ dtack wr/r\ w locx2 corsigb sec8k clkx1 fsync clkx2/clkx2po clkx2pi io_vss clkx2no clkx2ni ref8kclk io_vdd_5v pllclk d15 d14 ring_vss ring_vdd_3v d13 d12 d11 d10 d9 d8 io_vss d7 d6 d5 d4 d3 io_vdd_5v d2 d1 d0 cs a1 ring_vss ring_vdd_3v a2 io_vss a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 a14 a15 aem io_vdd_5v io_vss io_vdd_3v mem_oe mem_wr2 mem_wr3 mem_cs1h mem_cs0h mem_dat24 mem_dat25 mem_dat26 io_vss mem_dat27 mem_dat28 io_vdd_3v mem_dat29 mem_dat30 mem_dat31 mem_par3 mem_dat16 io_vss mem_dat17 core_vss core_vdd_3v mem_dat18 mem_dat19 io_vdd_3v mem_dat20 mem_dat21 mem_dat22 mem_dat23 mem_par2 io_vss
mt90500 27 240 pin pqfp 120 102 104 106 108 110 114 116 118 112 52 54 56 58 60 50 48 46 44 42 40 38 36 34 32 100 82 84 86 88 90 94 96 98 92 80 62 64 66 68 70 74 76 78 72 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 freerun corsiga corsigc corsigd corsige ic intel/ motorola ptxdata0 ptxdata1 ring_vss ring_vdd_3v io_vdd_5v io_vss ptxdata2 ptxdata3 ptxdata5 ptxdata6 ptxdata7 ptxpar ptxen ptxsoc ptxclav prxclav prxen prxsoc prxdata7 prxdata6 prxdata5 io_vdd_5v io_vss prxdata2 prxdata3 prxdata4 prxdata1 prxdata0 stxclav stxen stxsoc stxdata7 stxdata6 stxdata5 stxdata4 stxdata3 stxdata1 stxdata2 stxdata0 reset prxclk ring_vss ring_vdd_3v ptxclk ex_8ka int stxclk io_vss mclk io_vdd_5v ic tristate io_vss io_vdd_3v tck trst tdi tdo tms memclk mem_add8 core_vss core_vdd_3v mem_add9 mempar0 mem_add10 mem_dat7 mem_dat6 mem_dat5 mem_dat4 mem_dat3 io_vss io_vdd_3v mem_dat2 mem_dat1 mem_dat0 mem_add11 mem_add12 mem_add13 mem_add14 io_vss io_vdd_3v mem_wr0 mem_wr1 mem_cs1l mem_cs0l mem_add7 io_vdd_3v mem_add6 mem_dat8 mem_dat9 core_vss core_vdd_3v io_vss mem_dat10 mem_dat11 mem_dat12 mem_dat13 mem_dat14 mem_dat15 io_vdd_3v mem_par1 mem_add5 io_vss mem_add4 mem_add3 mem_add2 mem_add1 mem_add0 mem_add17 mem_add16 mem_add15 ptxdata4
mt90500 28 4. functional description as shown in figure 1, mt90500 block diagram, on page 12, the mt90500 device consists of the following major components: tdm module, external memory controller, tx_sar, rx_sar, utopia module, clock recovery, microprocessor interface, and test interface. this section describes each module in detail. 4.1 tdm module this circuit module is the interface to the time division multiplexed (tdm) buses, which carry n x 64kbps data. the tdm module interfaces are: ? 16 bidirectional tdm data streams on pins st[15:0]; these pins can be con?gured through soft- ware registers to support various bus formats (st-bus, mvip, h-mvip, scsa, or idl) and data rates of 2.048 mbps, 4.096 mbps, or 8.192 mbps; (for the selection of the bus type, see tdm bus type register at address 6010h in section 5.) ? the tdm bus clocks (clkx2, clkx1) and frame synchronization signal (fsync); ? the tdm bus ancillary signals such as sec8k (mvip) and clkfail (scsa); ? a local tdm bus (locx2, locx1, lsync, locsti, and locsto); the format of the bus, which runs at 2.048 mbps (locx2 = 4.096 mbps), is user-programmable via software (see local bus type register at address 6020h). the tdm module moves tdm data from the tdm serial inputs to the external memory (where it is read by the tx_sar) in the transmit direction, and from the external memory (where it was written by the rx_sar) to the tdm outputs in the receive direction. this is done with the aid of an internal tdm frame buffer, which is used to buffer 4 frames of each tdm channel in both directions; i.e. four frames in the receive direction (atm to tdm), and four frames in the transmit direction (tdm to atm). the tdm module can be divided into four main processes: ? tdm clock logic, which controls all the operations related to clock generation and clock signal monitoring on the tdm bus; ? tdm interface operation, which controls the input and output of the serial tdm data; ? tdm data to external memory process, which transfers tdm input data into transmit circular buffers in the external memory; ? external memory to tdm data output process, which transfers tdm output data from receive circular buffers in the external memory to the tdm output bus. each of these processes are described in detail below. 4.1.1 tdm clock logic the tdm clock logic controls all of the operations related to clock generation and clock signal monitoring on the tdm bus. the block diagram of the tdm clock logic is shown in figure 3. this module consists of several blocks, including: selection logic for an 8 khz reference for the external pll (ref8kclk), the main tdm bus clock generation logic, the local tdm bus clock generation logic, the clock drivers & clock selection for the sec8k signal, and the clock failure detection logic. 4.1.1.1 tdm timing modes the mt90500 supports 4 major tdm timing modes. there are also a number of tdm timing features which are independent of the tdm timing mode being used: ? the sec8k pin (mvip compatibility) can be programmed as either output or input. the sec8ken bit in the mcgcr register (6090h) enables the sec8k pin driver. if the sec8k pin is enabled as an output, the sec8ksel bit in the same register selects the source for this signal (the ex_8ka input, or the internal 8 khz fs_int signal which is derived from clk16).
mt90500 29 ? the clkx2 signal can be selected as single-ended or differential. (differential clkx2 allows com- patibility with the h-mvip bus.) in tdm timing slave, the clkx2 signal can be input on the clkx2 pin, or the differential clkx2pi and clkx2ni pins. this selection is made with clktype in the tdm bus type register at address 6010h. in tdm timing master, the clkx2 signal is output on the clkx2/clkx2po pin, and an inverted clock is available on the clkx2no pin. the mt90500 supports the following tdm timing modes: ? tdm timing bus sla ve - clkx2 ref erence (clkmaster = 0 in tdm bus type register at 6010h) in this mode, the mt90500 is con?gured as a tdm timing slave and all internal tdm timing is synchronized to the tdm clock inputs: clkx2, clkx1, and fsync. the following sub-modes are also selectable: ? the clkx1 can be an input at the clkx1 pin, or it can be derived internally from clkx2. this is controlled by tclksyn (address 6010h). if the clkx1 pin is not used as an input in tdm slave mode, it remains high-impedance. ? tdm timing slave operation takes its 8 khz framing from the fsync input pin, which would usu- ally be driven by the tdm bus. to support other implementations, the ref8kclk output remains active in tdm slave mode. an 8 khz reference output can be made available at ref8kclk, selectable from the ex_8ka input, the sec8k pin, or one of the internal dividers. in addition, the freerun output can be used to monitor the presence of ref8kclk. main tdm bus timing and clock generation logic 0 1 2 3 external pll (optional) clkx2 fsync ex_8ka mclk rxvclk ref8kclk 0 1 pllclk sec8k 0 1 figure 3 - tdm clock selection and generation logic clkx2 clkx1 fsync master/slave clock absent detection logic sec8ken freerun local tdm bus clock generation logic locx2 locx1 lsync local tdm bus main tdm bus mt9041 or other pll clk16 0 1 sec8k_int ex_8ka_int refsel<1:0> divclk_src bepll sec8ksel adaptive clock recovery atm cells divide by 2 to 16384 divide by 1,2,4,or 8 fsync ex_8ka_int ref8kclk detection logic external cpu bus internal cpu bus fs_int fs_int div1...8 phlen square square sec8k_sq ex_8ka_sq all control bits shown are in master clock generation control register (6090h). 10 1 0 (16.384 mhz) clkx1 mt90500 srts clock recovery fnxi srts
mt90500 30 ? tdm timing bus master - freerun (clkmaster = 1 in tdm bus type register at 6010h) in this mode, the mt90500 is con?gured as the tdm timing master and the mt90500 drives the three tdm bus clocks: clkx2, clkx1, and fsync. the mt90500 clock generator block uses either the mclk input or the pllclk input to generate all of the required clocks. typically in this mode mclk or pllclk is connected to an oscillator, and no other synchronization source is used. several selections must be made: ? the selection of mclk or pllclk is determined by the bepll bits in the master clock genera- tion control register at 6090h. ? the selected clock is divided by 1, 2, 4, or 8 to obtain a 16.384 mhz clock, called clk16. this divi- sion is controlled by the div1...8 bits at 6090h. ? tdm timing bus master - 8 khz ref erence (clkmaster = 1 in tdm bus type register at 6010h) in this mode, the mt90500 is con?gured as the tdm timing master and the mt90500 drives the three tdm bus clocks, synchronized to one of several possible 8 khz references. typically, in this mode, the pllclk input is driven by an external pll (such as the mitel mt9041), which is controlled by the ref8kclk and freerun outputs. the following options are also selectable: ? one of four 8 khz reference sources must be selected, using the refsel bits at 6090h. (see figure 3 and section 4.1.1.2 for further details.) ? if the external pll is controlled by the freerun output pin, the pins operation must be speci?ed by the freerun bits at 6090h. the cpu can force the freerun pin to either state, or allow the freerun pin to follow the ref8kclk failure-detection bit (reffail at 6082h). ? bus master -alternate (clkmaster = 0, clkalt = 1 in tdm bus type register at 6010h) in this mode, the mt90500 is con?gured as a tdm timing slave, but stands ready to become the timing master, should the timing on the tdm bus fail. the switch is normally automatic (based on the clkfail input), but can also performed by the cpu (for instance: by programming the chip into tdm timing master following a clock absent interrupt). the following options are also selectable: ? to make the switch from alternate to master automatic, several settings are required: clkalt at 6010h is set high, and the corsiga pin is con?gured as the clkfail input (corsigacnf = 11 at 6004h). ? the master-alternate operates normally as a tdm timing slave, and has the same options as the tdm timing slave listed above. ? the master-alternate can be set up to switch to master-freerun operation, should the tdm bus clocks fail. the same options as listed above for master-freerun apply to this mode. ? the master-alternate can be set up to switch to master-8 khz reference operation, should the tdm bus clocks fail. the same options as listed above for master-8 khz reference apply to this mode. additionally, ref8kclk can be obtained from the tdm bus by dividing clkx2. this allows the external pll to be phase-locked to the tdm bus clocks. note that in this case the freerun output should be set up to automatically place the external pll in freerun should the tdm bus clocks fail. ? the internal 8 khz (fs_int) of the master-alternate can be phase-locked to the tdm bus fsync by setting phlen = 1 at 6090h. (this is only valid when the fsync type at 6010h is set to 00.) this will align the internal stand-by fsync, clkx2, and clkx1 to the tdm bus to within a clock cycle of the internal 16.384 mhz clock, allowing for minimal phase-shift should the master-alter- nate mt90500 take over the tdm bus clocks. 4.1.1.2 ref8kclk selection logic the ref8kclk output pin of the mt90500 is intended to provide a clock reference to an optional external pll. this signal would usually be an 8 khz frame pulse, but other signals are possible. the external pll (e.g. mitel mt9041) can be used to multiply the ref8kclk output to 16.384 mhz (or 32.768 mhz) and attenuate jitter. the 16.384 mhz can then be applied to the pllclk input pin to allow the mt90500 to generate the tdm
mt90500 31 clocks: clkx2, clkx1 and fsync. the source for the ref8kclk signal is selected via the refsel bits at address 6090h. the four possible sources for ref8kclk are: ? a clock input signal pin operating at 8 khz (ex_8ka) ? a secondary 8 khz reference from the tdm bus (sec8k, compatible with mvip/h-mvip) ? a freerun mode clock, which is a divided-down version of clkx2 or mclk; selected by divclk_src in register 6090h, and divided as speci?ed in register 6092h ? rxvclk, a more precisely divided-down version of mclk from the adaptive clock recovery block. the division is controlled by registers 60a8h and 60aah. the ref8kclk signal is made available on the output pin whether the mt90500 is programmed to be tdm timing master or slave. also included in the mt90500 is circuitry to convert the sec8k signal and the ex_8ka signal into square waves. if the sec8k_sq control bit in register 6090h is set high, internal logic will convert the sec8k input signal into a square wave before passing it to the ref8kclk selection multiplexer. the ex_8ka_sq bit controls the squaring function for the ex_8ka signal. see the register 6090h. mitel plls will typically work with either a pulse 8 khz, or a square 8 khz, but other pll implementations may require a square 8 khz reference input. 4.1.1.3 main tdm bus timing and clock generation logic when the mt90500 is in the tdm timing master mode, this logic generates the main tdm bus clocks (clkx2, clkx1, and fsync). this block receives clk16 (a 16.384 mhz clock which is a divided-down version of either pllclk or mclk, as set in register 6090h) and outputs the generated tdm bus clocks. by programming the appropriate software registers (i.e. tdmtyp at address 6010h), the generated signals can be 16.384mhz/ 8.192mhz/4.096mhz, 8.192mhz/4.096mhz/2.048mhz, and 8 khz respectively. additionally, the tdm bus clock generation logic generates a source signal to the sec8k output line when the sec8ken register bit is enabled. when in tdm timing slave mode, or in master-alternate mode, this logic generates an internal stand-by 8 khz signal (fs_int), from the clock selected by bepll in register 6090h. this can be driven out on sec8k if enabled by sec8ken. 4.1.1.4 tdm clock drivers if the mt90500 is the tdm timing master, this block enables the clock drivers for clkx2, clkx1, and fsync. if the mt90500 is in slave mode, the drivers are disabled and clkx2, clkx1, and fsync are inputs to the mt90500. in slave mode, the clkx1 source can be separately selected between the clkx1 input or internally provided clkx2/2. these options are controlled by the tdm bus type register at 6010h. 4.1.1.5 clock failure detection there are three status bits related to the detection of clock failure: reffail (6082h), and cabs and cfail (6002h). these bits will cause an interrupt if their respective enable bits are set (reffailie at 6080h, and cabsie and cfailie at 6000h) and the tdm_inte bit is set at 0000h. the reffail bit monitors the absence of the ref8kclk signal. when this signal is absent, the clock detect logic can activate the freerun output signal which is used to place the external pll in freerun mode. once the ref8kclk signal goes back to normal (due to the cpu changing the timing source), the cpu can disable the freerun output signal by clearing the reffail bit in the clock module general status register at 6082h. with proper selection of the external pll, this clock failure detection circuit can help to guarantee that the tdm clocks do not glitch when the ref8kclk reference to the external pll changes. the cabs bit indicates that one or more of the tdm bus clock signals (clkx2, clkx1, or fsync) are absent. this block uses mclk to check for activity on the above signals. in the case of clock absence, the clock absent (cabs) bit in the tdm interface status (tis) register at address 6002h is activated. the cfail bit monitors the clkfail pin (a scsa bus signal) and requires that the corsiga pin be con?gured as the clkfail input. if the clkfail input goes high when the mt90500 is operating in master- alternate mode (clk_alt at 6010h), the mt90500 will take over the tdm bus and become the master tdm clock source (see the bus master-alternate description in section 4.1.1).
mt90500 32 4.1.2 tdm interface operation 4.1.2.1 main tdm bus operation the main tdm bus (pins st[15:0]) supports scsa, mvip, h-mvip, st-bus, and idl protocols. these buses have different frame sync pulse orientations and different data sampling speci?cations, as well as different pin requirements. however, all of these buses are composed of 16 data pins, as well as clkx2, clkx1, and fsync lines. the tdm bus type is controlled by the tdm bus type register at 6010h. in all bus types, outputs change on the rising edge of clkx1. inputs can be sampled at the 2/4, 3/4 or 4/4 point of the clkx1 signal. mvip/scsa/ st-bus all use a negative fsync that is asserted for one clkx2 cycle, straddling the frame boundary. the idl bus uses a positive fsync which is asserted for one cycle of clkx1, preceding the frame boundary. (see figure 39, nominal tdm bus timing, on page 114.) 4.1.2.2 tdm loopback the general output enable bit (genoe in the tdm interface control register at 6000h) is used to enable data to be driven out on the tdm output streams. when this bit it not set (i.e. it is low), the internal tdm transmit buses are connected to the internal tdm receive buses (while the internal tdm buses are disconnected from the external tdm buses) giving a tdm loopback from atm receive back to atm transmit. in this mode, the internally-generated tdm clocks and synchronization signals are used. this allows the user to test the mt90500 in stand-alone mode by passing receive atm cells through the sar, through the internal loopback at the tdm interface, and back through the sar and out as transmit atm cells. 4.1.2.3 per-channel output enable feature the st[15:0] pins are bidirectional, and are able to switch between input and output directions on a per- channel basis. the output enable registers located at addresses 7000 + 2n (n = 0, 1, ..., 127) are used for individual time slot output enable control. depending on the tdm bus rate, up to 128 registers (256 bytes) are used to provide up to 2048 individual channel-output-enable bits. at 2.048 mbps, 32 registers are used; at 4.096 mbps, 64 registers are used; and at 8.192 mbps, 128 registers are used. during each channel period (tdm time slot), 16 output enable bits (one register) are read from the output enable registers. within each frame, 32, 64, or 128 registers are read (depending on the tdm bus rate). the genoe bit must be set high, as well as the individual channel-output-enable bit, in order for a tdm channel to be transmitted from the mt90500 onto the tdm bus. in order to prevent data collisions on the tdm bus, the user should clear all output enable register bits for channels not used as outputs, prior to setting the genoe bit. the genoe signal, when inactive, asynchronously deactivates the tristate buffers on the data pins and routes the output paths back into the input paths, causing the tdm bus to enter the tdm loopback mode (see section 4.1.2.2). since the st pins are bidirectional, the input sampling is always active and output data can be re-sampled back into the mt90500. this re-sampling is used when locsti channels are output on a st pin and then re- sampled for atm transmission, when st outputs are re-sampled for transfer to the locsto pin, or for test and veri?cation purposes. 4.1.2.4 local bus operation the local bus signals are: ? locx2, locx1, lsync - clock output signals; ? locsti, locsto - local serial tdm data in and data out. the mt90500 provides three output clocks for the local tdm bus: locx2, locx1 and lsync. these clocks are derived from clkx2, and controlled by the relevant bits in the local bus type register (register 6020h). the lclkdiv bits allow locx2 to be equal to clkx2, clkx2 / 2, or clkx2 / 4 (note that the local bus rate is 2.048 mbps, which is always equal to, or less than, the main tdm bus rate). also in register 6020h are the control bits to select the lsync frame-pulse type, the routing of tdm streams onto and from the local bus, and the locsti sampling point.except for the rate, the local bus type can be con?gured independently of the main tdm bus type.
mt90500 33 4.1.2.5 local bus data transfer process a local bus data transfer process is provided, which allows local serial tdm input (locsti) data to be output on the main tdm bus (st[15:0]) in place of the usual data from the internal frame memory. similarly, data from the main tdm bus can be routed directly onto the local tdm output (locsto), without affecting the tdm to internal frame memory transfer. the local bus pins on the mt90500 are an extension of the main tdm bus. the data on any stream of the main tdm bus may be passed to the local bus output (locsto). the source pin (one of st[15:0]) is controlled with the sti2locsto bits at 6020h, and the time slots to be transferred are indicated by the tdm bus to local bus transfer register (6022h). note that this tdm data can be from two sources: either externally-sourced data being driven into the selected st pin, or data from the atm link being driven out by the rx_sar, and copied to the locsto pin. when fewer than the maximum number of available time slots are transferred between the main tdm bus and the local bus, the unused locsto output time slots are ?lled with data fed back internally from locsti. similarly, the data input on locsti may be passed to any stream of the tdm bus as indicated by the local bus to tdm bus transfer register (6024h), and the locsti2sto bits at 6020h. note that when the local bus to tdm process is enabled, from 1 to 32 data bytes from the rx_sar will be replaced by local bus data. the enable bits for the main tdm bus channels are the normal bits in the output enable registers (7000h + 2n). data from the locsti input pin can be transferred to the atm link through the tx_sar, by re-sampling the channels on which the local bus data is output as inputs to the tx_sar. 4.1.3 tdm data to external memory process 4.1.3.1 general the segmentation of serial tdm input data into atm cells starts by copying the tdm data into transmit circular buffers. the data is then read out of the transmit circular buffers by the tx_sar (see section 4.3.2, tx_sar process, on page 48). the initial step of copying the serial tdm input data into the transmit circular buffers is performed by the tdm data to external memory process described in this section. all of the serial tdm input data available on the tdm buses is ?rst written to an internal frame buffer which holds 4 frames of tdm data per input channel. as shown in figure 4, this internal frame memory (which is used in both the receive and transmit directions simultaneously) is used as a pingpong buffer. while one page of the memory is being loaded with input tdm data, the other page of the memory is being transferred to the transmit circular buffers in external memory. this transfer occurs every 500 m s (4 frames * 125 m s per frame). tdm input frame buffer internal memory tdm buses external memory each active ds0 channel occupies a 64-byte transmit circular buffer. figure 4 - tdm frame buffer to external memory transfer txcbbase (register 6044h) txcbbase+64 txcbbase+128 tx circular buffer 1 tx circular buffer 2 tx circular buffer n-1 tx circular buffer n tx circular buffer 3
mt90500 34 4.1.3.2 transmit circular buffer control structures to minimize the amount of external memory required for the tdm data to external memory process, only the tdm channels assigned to be transmitted over the atm link are transferred to external memory. each tdm channel to be transmitted over the atm link occupies a 64-byte transmit circular buffer in external memory. as shown in figure 5, the mt90500 fetches control data from the transmit circular buffer control structure in external memory in order to determine which tdm channels to transfer to external memory and where to put the data. the transmit circular buffer control structure is a sequential control table consisting of 16-bit entries: ? bit<15> indicates that the entry is valid (active high). ? bits<14:11> are not used, and should be set to zeroes. ? bits<10:0> identify a channel number. ? bits<10:4> identify a tdm channel within a stream. the channels are numbered from 0 to 127. ? bits<3:0> identify a stream number, from 0 to 15. the ?rst entry in the transmit circular buffer control structure tells the hardware from which tdm channel it will ?ll the ?rst 64-byte transmit circular buffer, the second entry tells the hardware from which tdm channel it will ?ll the second transmit circular buffer, and so on. if the entry is not valid (i.e. the v bit is not asserted), the transfer is not executed. in order to prevent unnecessary transfer of tdm data to external memory, the user should zero-out all unused entries within the tx circular buffer control structure. 0 4 15 12 21 v txcbcsbase txcbcsl time slot v v v v v +000 +002 +004 +006 maximum of 2048 entries txcbcs tdm channels control data minimum of 128 entries (i.e. words) v = entry valid (bit<15>) r = reserved (bits<14:11> - set to all zeroes) time slot = 7-bit tdm time slot select (bits<10:4>) stream = 4-bit tdm stream select (bits<3:0>) r r rr rr stream time slot stream time slot stream time slot stream time slot stream time slot stream +ffe 3 <8:0> <20:9> 6040h <20:0> pointer to start of control structure r r r 9 tx circular buffer 40 10 15 r r r b 0_0000_0000 figure 5 - transmit circular buffer control structure internal memory external memory r r r r r r r r r r r r
mt90500 35 4.1.3.3 transmit circular buffers the location of the transmit circular buffers in external memory is determined by txcbbase (tx circular buffer base address), found in register 6044h. the ?rst transmit circular buffer is located at txcbbase. the second is located at txcbbase + 64, the third at txcbbase + 128, etc., as seen in figure 4. all transmit circular buffers are 64 bytes long, so buffer addresses are not included in the control structure but are considered to follow each other linearly, one after the other, corresponding to the order of the entries in the control structure. therefore, if the base address of the tx circular buffers was 10000h (as de?ned by the txcbbase entry at 6044h), the ?rst entry in the control structure (be it valid or not) would correspond to the buffer at 10000h, the next to 10040h, the one after to 10080h, etc. the last step of the tdm data to external memory process transfers data from the internal frame buffer to the transmit circular buffers in external memory. the write pointer to all transmit circular buffers is a single 8-bit counter that increments every four frames as the internal to external memory transfer is performed. the 4 least signi?cant bits in this counter are used as the tdm circular buffer write pointer. all the desired tdm channels in the internal frame buffer will be transferred into the transmit circular buffers as speci?ed by the transmit circular buffer control structure. note that the transmit circular buffer control structure must be initialized before the internal/external memory process is enabled (via the ieena bit in register 6000h). 4.1.4 external memory to tdm data output process 4.1.4.1 general the reassembly of received cbr (constant bit rate) atm cells into serial tdm output data is completed by reading the data out of receive circular buffers and placing the data on the tdm outputs. the data is written to the receive circular buffers by the rx_sar (see section 4.4.2, rx_sar process, on page 57). then the reading of serial tdm output data from the receive circular buffers is performed by the external memory to tdm data output process. this process will be outlined here. the same internal frame buffer used in the tdm data to external memory process is used to buffer the received data to be transferred to the tdm output bus. as shown in figure 6, this internal frame buffer holds 4 frames of output data for each tdm channel (to a maximum of 2,048 channels). this frame buffer is used in a pingpong scheme where alternately half the memory is used to transfer data to the tdm buses while the other half is being used to transfer data from the external memory. tdm data is transferred from the receive circular buffers in external memory to the internal frame buffer. as in the tdm data to external memory process described previously, the pointer to all receive circular buffers is a single 8-bit counter that increments every four frames as the external to internal memory transfer is performed. the least signi?cant 4 to 8 bits of the counter are used as the tdm circular buffer read pointer, depending on the size of the receive circular buffers. tdm output frame buffer tdm buses internal memory external memory figure 6 - external memory to tdm frame buffer transfer rx circular buffer 1 rx circular buffer 2 rx circular buffer n-1 rx circular buffer n rx circular buffer 3 each active ds0 channel occupies a programmable-size receive circular buffer (64, 128, 256, 512, or 1024 bytes)
mt90500 36 4.1.4.2 external memory to internal memory control structures to know which internal frame buffer tdm channels need to be written (generally, only the tdm channels scheduled for transmission on the tdm bus), the mt90500 uses control data from the external to internal memory control structure. the external to internal memory control structure is located in external memory, and is depicted in figure 7. the control data in the external to internal memory control structure tells the hardware where in external memory the receive data is located (rx circ. buf. address), the size of the receive circular buffer used, and to which tdm channel (tdm channel #) this data must be written. the external to internal memory control structure uses a 32-bit control word, as indicated below and in figure 7: ? bit<15> - v - valid bit. if high, indicates that this entry is valid, and the associated receive circular buffer is active. if an entry is not valid, it is simply bypassed and the next entry is read. ? bit<14> - d - write-back disable bit. if high, the receive tdm data will be left unaltered in the receive circular buffer. if low, ffh will be written over each byte of the receive tdm data once it has been transferred to the internal frame memory. (this has the effect of putting ffh - silence - on the tdm bus if the receive circular buffer underruns and the same byte is read again before new tdm output data is written to the receive circular buffer by the rx_sar.) ? bit<13> - u - tdm read underrun detection enable. if this bit is high, and the external memory to internal memory process tries to transfer a byte which has already been transferred, an underrun event is detected and an interrupt may be generated. see registers 6000h, 6002h, 6046h and 6048h. this bit (and tdm read underrun detection circuit) work independently of the state of the d bit. if this bit is written low, tdm read underrun detection stops for this tdm channel on the present tdm frame. ? bits<12:11> - r - not used. ? bits<10:0> - tdm channel # - identi?es a destination tdm channel number and stream ? bits<10:4> identify a tdm channel within a tdm stream. the channels are numbered from 0 to 127. ? bits<3:0> identify a tdm stream number, from 0 to 15 (corresponding to the st[0:15] pins). ? rx circ. buff. address and size - indicates the receive circular buffer address, and the size of the receive circular buffer (64, 128, 256, 512, or 1,024 bytes). the leading bits in the ?eld, when appended by a number of least-signi?cant zeroes, indicate the receive circular buffer address. the total number of bits representing an address should be 21 bits. for example, for a 128-byte buffer, the 14-bit address given in the structure will be appended by 7 zeroes, resulting in a 21-bit address. it is important to consider this control structure when determining the location of receive circular buffers in external memory. examining the con?guration shown in figure 7 on the next page, it can be seen that the number of bits available to identify the address of receive circular buffers differs depending on the size of the buffer. due to this restriction, it is essential that each buffer be located only on a boundary corresponding to the size of the buffer (i.e. 64-byte buffers must be located on 64-byte boundaries, 128-byte buffers must be located on 128-byte boundaries, and so on...). once all of the entries have been scanned, the internal frame memory is ?lled and the external memory to internal memory process terminates. if the process is still active four frames after being started, a tdm out of bandwidth error (found in the tdm interface status register at 6002h) is generated. the ?nal step is for the mt90500 to drive the tdm data out on the tdm pins, st[15:0]. since not all time slots are designated as outputs, separate output enable registers located at addresses 7000 + 2n (n = 0, 1, ..., 127) are used for individual time slot output enable control. in addition, the genoe bit in the tdm interface control register at 6000h must be set high to enable the general internal memory to tdm output process (see section 4.1.2.3 for more details).
mt90500 37 11 15 0 10 0 4 15 21 12 eimcsbase eimcsl b 0_0000_0000 +000 +004 maximum of 2048 entries figure 7 - external memory to internal memory control structure 0 15 1 rx circular buffer address (15 bits) address bits<20:6> 0 15 10 0 15 100 0 15 1000 0 15 10000 structure of the receive circular buffer address and size fields 6042h emim <8:0> <20:9> 128 bytes 64 bytes 256 bytes 512 bytes 1024 bytes <20:0> +1ffc +002 +006 +00a tdm channel # rx circ. buff. address & size v d u v d u +008 v d u rx circ. buff. address & size rx circ. buff. address & size +1ffe rx circ. buff. address & size v d u tdm channel # tdm channel # tdm channel # r r r r pointer to start of control structure external to internal memory 9 minimum of 128 entries internal memory external memory rx circular buffer address (14 bits) address bits<20:7> rx circular buffer address (13 bits) address bits<20:8> rx circular buffer address (12 bits) address bits<20:9> rx circular buffer address (11 bits) address bits<20:10>
mt90500 38 4.2 external memory controller the external memory controller block of the mt90500 resides between the internal blocks and the external memory. it receives memory access requests from the internal blocks (tdm interface, tx_sar, rx_sar, utopia, and microprocessor modules) and services them by reading data from, or writing data to, the external memory. the mt90500 pins connecting to the external memory consist of: 18 address bits (mem_add[17:0]), 4 memory bank/chip selection bits ( mem_cs[1:0][h/l]), 32 data bits (mem_dat[31:0]), 4 parity bits (mem_par[3:0]) used as tdm read underrun ?ags, 4 write enable bits ( mem_wr[3:0]), a memory output enable bit ( mem_oe), and a memory clock (memclk). the external memory controller block ensures the proper timing of all memory signals and the ?ow control of the external memorys data bus. the external memory controller block also converts a 21-bit internal byte-oriented address to a memory bank selection and a physical address. (the 2 lsbs select one byte within the 4-byte/double-word wide data bus, up to 18 bits select a particular double-word address, and the msb selects one of two possible memory banks.) the external memory controller block implements memory accesses to an external 36-bit synchronous static random access memory (ssram or sync sram). it supports one or two banks of external memory, each bank having a total capacity ranging from 32k x 36 bits to 256k x 36 bits. thus the mt90500 can operate with external memory ranging from 128 kbytes to 2,048 kbytes. the external memory controller can interface with several different types of sync sram, but they must support synchronous bus enabling. synchronous bus enabling means that the sync sram chip must only enable its data output buffers one cycle after a read (two cycles for pipelined ssram), regardless of the state of the asynchronous output enable pin ( mem_oe). a read is indicated by mem_wr[3:0] all high, and the appropriate mem_cs[1:0][h/l] asserted. the ssram must also support single cycle writes (early write, or adsc type writes). the ssram can be a registered-input type (synchronous, synchronous flow-through, or synchronous burst) or a registered-input/registered-output type (synchronous pipelined). although the mt90500 uses the synchronous access feature of these memories, it does not use the burst access features of these memories, since most mt90500 memory accesses are random rather than sequential. although write accesses to synchronous sram and to synchronous pipelined sram are identical, there is a difference in the number of clock cycles before data is returned on the data bus during read accesses. the mt90500 supports memories with 1, 2 and 3 stages of pipelining (see figure 8). both 18-bit and 36-bit data bus memories are supported, but in the ?rst case, two chips must be used in parallel to form a 36-bit data bus. also, two 36-bit wide memory banks can be joined to double the memorys capacity (see figure 9). table 9 lists most of the possible memory size combinations. (note: 16-bit and 32-bit memories can be used, but in that case the tdm read underrun indication will not be available.) all chips used must be of the same type. address1 readlen = 1 (flow through) readlen = 2 readlen = 3 (pipelined) note: the number of clock cycles between an address (address1) and its read data (data1) is set according to readlen in the memory configuration register at address 0040h. values greater than 3 are reserved. figure 8 - memory read pipeline length clock address address2 address1 captured data data1 data1 data1
mt90500 39 figure 9 - logical byte address vs. physical address and memory banks note: the addressing mode, which indicates the number of address lines connected to the external memory, is selected via the addmode<1:0> bits in the memory con?guration register (0040h). cpbank in the same register indicates the number of memory chips per bank. because of the bidirectional data bus, some synchronous sram devices may require a turnaround cycle. the mt90500 can be programmed to insert a turnaround cycle between a read access and a write access, as required (see figure 10). similarly, the mt90500 can be programmed to insert a turnaround cycle between a read access and a read access to the other memory bank. some memories have an output disable time that is shorter than the output enable time (so a turnaround cycle between reads to different banks is not necessary), meanwhile other memories require a turnaround cycle. this type of turnaround cycle is illustrated in figure 11. byte address 32k addressing mode mem_add[14:0] 64k addressing mode mem_add[15:0] 128k addressing mode mem_add[16:0] 256k addressing mode mem_add[17:0] 0 - 128k bank 1 32k*4bytes bank 1 64k*4bytes bank 1 128k*4bytes bank 1 256k*4bytes 128k - 256k bank 2 32k*4bytes 256k - 384k bank 2 64k*4bytes 384k - 512k 512k - 640k bank 2 128k*4bytes 640k - 768k 768k - 896k 896k - 1024k 1024k - 1152k bank 2 256k*4bytes 1152k - 1280k 1280k - 1408k 1408k - 1536k 1536k - 1664k 1664k - 1792k 1792k - 1920k 1920k - 2048k table 9 - memory size combinations total memory size external memory address lines used (double-word address) memory addressing mode memory chip size bank 1 memory chip size bank 2 64 kbyte 13:0 32k 64 kbyte 128 kbyte 14:0 32k 128 kbyte 192 kbyte 14:0 32k 128 kbyte 64 kbyte 256 kbyte 14:0 15:0 32k 64k 128 kbyte 256 kbyte 128 kbyte 384 kbyte 15:0 64k 256 kbyte 128 kbyte 512 kbyte 15:0 16:0 64k 128k 256 kbyte 512 kbyte 256 kbyte 768 kbyte 16:0 128k 512 kbyte 256 kbyte 1024 kbyte 16:0 17:0 128k 256k 512 kbyte 1024 kbyte 512 kbyte 1536 kbyte 17:0 256k 1024 kbyte 512 kbyte 2048 kbyte 17:0 256k 1024 kbyte 1024 kbyte
mt90500 40 it should be noted that turnaround cycles, in effect, restrict the memory bandwidth, and therefore the operation of the mt90500. maximum throughput is achieved with full clock speed on the mclk input (which drives memclk), and with non-pipelined synchronous sram without turnaround cycles (easiest achieved by using a single bank). maximum throughput is only required in applications requiring a full 1024 transmit tdm and 1024 receive tdm channels and extra cpu accesses for data or frequent setup. data no turnaround cycle (flow-through ssram) data 1 turnaround cycle (flow-through ssram) figure 10 - read / write turnaround cycles memclk mem_csnx memclk mem_wr mem_wr address mem_csnx address data no turnaround cycle (pipelined ssram) memclk mem_csnx mem_wr address read 1 read 2 write 1 write 2 read 1 read 2 read 1 read 2 write 1 write 1 read address1 read address2 write address2 write address1 read address1 read address2 read address1 read address2 write address1 write address1 data 1 turnaround cycle (pipelined ssram) memclk mem_csnx mem_wr address read 1 write 1 read address1 write address1
mt90500 41 all of the above features are programmable by the software controlling the mt90500. the memory con?guration register (0040h) must be set before any memory process can be enabled. before any accesses are done to the external memory, the rrta, rwta, readlen, cpbank and addmode ?elds in this register must be written and must represent the actual memory con?guration. figure 11 - read / read turnaround cycles data no turnaround cycle (flow-through read) data 1 turnaround cycle (flow-through read) memclk mem_cs0x memclk mem_cs1x mem_cs1x address mem_cs0x address data 1 turnaround cycle (pipelined read) memclk mem_cs0x mem_cs1x address bank 0 bank 0 bank 0 bank 0 bank 1 bank 1 bank 1 bank 1 bank 0 bank 0 bank 0 bank 0 bank 1 bank 1 bank 1 bank 1 bank 1 bank 0 bank 0 bank 1
mt90500 42 4.3 tx_sar module 4.3.1 tx_sar overview 4.3.1.1 general the tx_sar block is responsible for performing cbr (constant bit rate) cell assembly functions from the tdm port towards the atm primary utopia interface, which is typically connected to a phy device. according to a user-programmable timing algorithm, the tx_sar circuit fetches data from the transmit circular buffers located in external memory and builds cbr atm cells (aal1, cbr-aal0, or cbr-aal5) which are subsequently transferred to the mt90500 internal utopia module and then to the primary utopia port. the tx_sar block has no direct interface to the pins of the mt90500, but ties together the tdm module and the utopia module. to construct cbr atm cells, which must be periodically formed at the correct rate, an event scheduler is used. to support different cell payload lengths and cbr aal types, three programmable event schedulers are provided by the tx_sar to manage the cell transmission timing. the tx_sar provides enough bandwidth to allow the transmission of 1024 channels. the rx_sar allows reception of 1024 channels simultaneously. (for a total device capacity of 1024 bidirectional channels - all 2048 tdm time slots.) the amount of external memory required to support the tx_sar process depends on the number of tdm time slots that need to be transmitted, as well as the number of simultaneous vcs. for example, the transmission of 1024 time slots over 1024 simultaneous vcs requires up to 100 kbytes of external memory for the tx_sar process. less memory is required if fewer vc connections or fewer tdm time slots are used. 4.3.1.2 supported atm cell formats the aal1 cell generation process supports tdm transport and trunking over standardized sdt (structured data transfer) with pointer bytes for up to n = 122 tdm channels; over pointerless structured data transfer for 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 even parity even parity vci clp cell with pointer 46 payload bytes figure 12 - aal1 atm cell format pti vci vpi vci gfc / vpi vpi hec sequence count pointer csi crc field payload byte #1 payload byte #2 payload byte #45 payload byte #46 vci clp cell without pointer 47 payload bytes pti vci vpi vci gfc / vpi vpi hec sequence count csi payload byte #1 payload byte #2 payload byte #46 payload byte #47 payload byte #3 crc field even parity
mt90500 43 n =1; and over partially-?lled cells (where n is less than, or equal to, the payload size). the cell parameters are con?gured through the microprocessor port. figure 12 gives examples of the atm aal1 cell formats. the mt90500 meets the itu i.363.1 standard for sdt for 1 to 96 octets per structure (1 to 96 tdm channels per vc). the mt90500 meets the ansi.630 standard for sdt for 1 to 122 octets per structure (1 to 122 tdm channels per vc). tdm traf?c over aal0 is also supported (referred to in this document as cbr-aal0). aal0 is the bare or null adaptation layer (5 bytes of header plus 48 bytes of direct user payload). figure 13 shows cbr-aal0 and aal1 partially-?lled cell formats. in addition, tdm traf?c over aal5 can also be transmitted (referred to in this document as cbr-aal5). the cell format for cbr-aal5 is shown in figure 14. the aal1 cell differs from the cbr-aal0 cell in that it contains an aal1 byte, and it may also contain a pointer byte. the aal1 byte contains a sequence count (0 to 7), a csi bit and the snp (sequence number protection) ?eld. the sequence count is used to identify cell ordering, and to aid in the detection of lost cells. the csi bit indicates the presence (csi = 1) or absence (csi = 0) of a pointer byte in even-numbered cells. in odd- numbered cells, the csi bits serve to carry the srts nibble. the pointer byte indicates the start of the next structure (since structures may be shorter or longer than 47 bytes, and therefore move through the aal1 payload). also worth noting is the high-order bit of the headers pti ?eld, which can be set to indicate an oam cell (a cell whose payload contains signalling rather than tdm data). the cbr-aal5 cell differs from aal1 and cbr-aal0 in that its tdm payload is 40 bytes (where tdm data can occupy 8, 16, 24, 32, or 40 payload bytes), and the remaining 8 bytes are devoted to aal5 overhead. every cell in a cbr-aal5 vc is an end-of-frame cell, as identi?ed by the lsb of the pti ?eld in the cell header being set. in addition, each cell contains a cpcs-uu byte and a cpi byte (both unused here), two length bytes and four crc bytes (all inserted by the mt90500). the mt90500 supports tdm trunking over aal5, for n = 1, 8, 16, 24, 32, or 40. for n = 1, the mt90500 meets the cell format in the atm forum standard af-vtoa-0083.000. 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 even parity vci clp partially-filled aal1 cell < 47 payload bytes figure 13 - partially-filled aal1 and cbr-aal0 cell formats pti vci vpi vci gfc / vpi vpi hec sequence count csi crc field payload byte #1 payload byte #2 pad byte or payload byte #46 vci clp cbr-aal0 cell 1 - 48 payload bytes pti vci vpi vci gfc / vpi vpi hec payload byte #1 payload byte #2 pad byte or payload byte #47 pad byte or payload byte #48 payload byte #3 payload byte #3 payload byte #4 pad byte
mt90500 44 1 2 3 4 5 6 7 8 figure 14 - cbr-aal5 cell format vci clp cbr-aal5 cell pti vci vpi vci gfc / vpi vpi hec payload byte #2 payload byte #3 payload byte #40 or pad byte cpcs-uu byte = 00 payload byte #4 payload byte #1 cpi byte = 00 length byte 1/2 = 00 length byte 2/2 = 8, 16, 24, 32, or 40 crc byte 2/4 crc byte 3/4 crc byte 4/4 - the least-significant bit of the pti field must be set high to indicate the presence of the crc-32 bytes (this bit indicates that this is the last cell of a data frame) - the mt90500 supports 8, 16, 24, 32 or 40 payload bytes. thus the mt90500 will support n =1 (payload = 8, 16, 24, 32 or 40 bytes) and n = 8, 16, 24, 32 or 40 (payload = n bytes) crc byte 1/4
mt90500 45 4.3.1.3 transmit event scheduler overview 4.3.1.3.1 introduction the distinctive characteristic of aal1, and the other constant bit rate techniques supported by the mt90500, is that they carry isochronous data, i.e. data that arrives at the sar at a constant rate. for aal1 nx64 (an aal1 vc carrying n tdm channels), the sar has to transmit exactly n bytes in atm cells for every n bytes that arrive in tdm frames. the tdm port delivers one byte for each of n tdm channels every frame, 8000 times a second. if on average the sar transmits less than, or more than, n * 8000 bytes/s the transmit circular buffer will eventually overrun or underrun (where on average is determined by the size of the transmit circular buffer). the mt90500 tx_sar meets this requirement by using schedulers that are tied to the tdm frame rate (125 m s). the mt90500 scheduler ensures that n bytes are sent out in atm cells for every frame of the tdm port. 4.3.1.3.2 fixed tdm payload schedulers the simplest case of constant bit rate traf?c is a vc using cells of ?xed tdm payload size. this includes ? cbr-aal0 cells, which always carry 48 tdm payload bytes or a ?xed partial-?ll tdm payload, ? aal1 n=1 cells, which always carry 47 tdm payload bytes or a ?xed partial-?ll tdm payload, ? partially-?lled cells, which always carry the same number of tdm payload bytes (4 to 47), ? cbr-aal5 cells, which always carry the same number of tdm payload bytes (8, 16, 24, 32 or 40). for a cell of constant tdm payload size m carrying n tdm channels, it can be seen that one cell of m bytes must be sent every m/n frames: tdm in = m/n frames * n bytes/frame = m bytes atm out = one m-byte cell = m bytes tdm in = atm out for this case of ?xed tdm payload size, we could create a scheduler that was m/n frames long, and program it to send one cell. let us consider a simple example (simpler than typically required of a mt90500 scheduler). if, for example, the sar was to carry 6 tdm channels (n = 6) in a cbr-aal0 48-byte cell (m = 48), we could use a 8 frame scheduler (48/6 = 8) with one cell event programmed: 8 frames * 6 bytes/frame = 48 bytes = one 48-byte cell if the transmit circular buffers are considered, it can be seen that after one frame the six transmit circular buffer will each contain one byte of tdm data. after two frames, each of the six transmit circular buffers will contain two bytes of tdm data. after 8 frames each of the six transmit circular buffers will contain eight bytes, enough tdm bytes to ?ll a 48-byte cell, therefore the scheduler is programmed send a 48-byte cell every 8 frames. for many values of n, however, m/n will not be an integer number of frames. so we could use a scheduler m frames long, and program it to send n cells (spread out over m frames). over m frames, with n bytes arriving each frame, the sar receives m * n bytes: tdm in = m frames * n bytes/frame = m * n bytes the sar will send n cells of m bytes: atm out = n cells * m bytes/cell = m * n bytes tdm in = atm out in our example of 6 tdm channels over cbr-aal0, we could use a 48 frame scheduler, programmed with 6 cell events: 48 frames * 6 bytes/frame = 288 bytes = 6 cells * 48 bytes/cell so over the course of 48 tdm frames the sar receives 288 tdm bytes, and the sar sends exactly 6 cells containing a total of exactly 288 bytes. the transmit circular buffers return to a constant level, and the scheduler meets the requirements for cbr. to support cbr-aal0, one of the mt90500 schedulers can be set to a length of 48 (long end = 47, long/short = 0), and n cell events programmed in. a typical application of the mt90500 would use a longer scheduler, set to a multiple of 48 (see below). to support aal1 n=1, (tdm payload m = 47) one of the mt90500 schedulers
mt90500 46 can be set to a length of 47 (long end = 46, long/short = 0), and programmed with one cell event, as we have described. a typical application of the mt90500 might have the ?rst of the three schedulers set this way to support aal1 n=1. it can be seen that for n not equal to one, we can program our cbr-aal0 scheduler a number of different ways. the most nearly constant cell rate will occur when we space the n cells evenly over the 48 frames. in our example of n = 6, we can send 6 cells together, wait 48 frames, send 6 cells, etc. but to achieve a more constant cell rate (to lower cell delay variation) we would want to send a cell and wait 8 frames, send another cell and wait 8 frames etc. by spacing the cell events 8 frames apart, our 48 frame scheduler example works identically to our 8 frame scheduler example. thus it is always desirable to space the n cells as evenly as possible over the scheduler (remembering that the end of the scheduler will wrap back to the beginning of the scheduler). it can be seen that where a scheduler of length m is required, a scheduler of length k*m may be used (k is an integer). in an m frame scheduler we would program n cell events, in a k*m scheduler we would program k*n events. this allows us to use one scheduler to support several different cell sizes m. in the mt90500, a scheduler may be up to 256 frames long. a scheduler of length 240 (long end = 239, long/short = 0), for example, supports cell sizes of 48, 40, 30, 24, 20,16, 12, 10, 8, and 5. a scheduler of length 160 (long end = 159, long/short = 0) supports cell sizes of 40, 32, 30, 20, 16, 10, 8, and 5. a typical application of the mt90500 might have the second of the three schedulers set to 240 or 160 to support various lengths of partially-?lled cells, cbr-aal0, and/or cbr-aal5. 4.3.1.3.3 aal1 long/short schedulers a scheduler for aal1 may need to be slightly more complex than a scheduler for cbr-aal0. when n is not equal to one, nx64 aal1 cells are not all of the same tdm payload size. when following the itu-t rec. i.363.1 standard, one cell in eight will carry a pointer. cells without pointers carry 47 tdm bytes, and cells with pointers carry 46 tdm bytes. (an aal1 sequence number byte is always present, completing the 48-byte atm cell payload.) although the individual cell length varies, the aal1 eight-cell sequence contains a constant 375 bytes of tdm payload (46 + 7 * 47 = 375) for an average tdm payload of 46.875 bytes per cell. for the aal1 case, we therefore wish to ?t the n tdm bytes per frame into the 375 tdm payload bytes of an eight-cell sequence, at a constant rate. we could create a scheduler 375 frames long, and program it to send n eight-cell sequences: 375 frames * n bytes/frame = 375 * n bytes = n eight-cell sequences * 375 bytes / eight-cell sequence or 375 frames * n bytes/frame = 375 * n bytes = n * 8 cells * 46.875 bytes/cell our scheduler of 375 frames length would be programmed for n * 8 cells, and achieve constant bit rate. it can be seen that we always program a multiple of 8 cell events into the scheduler, (n * 8 cells) this means that we can take a short-cut, and divide everything by 8. the schedulers in the mt90500 can be said to fold the 375 frames into 8 turns of the long/short scheduler (1 short turn of 46 frames, and 7 long turns of 47 frames). instead of programming n * 8 cells into the 375 long scheduler, we program n cells into the 375/8 scheduler: (7 turns * 47 frames/turn + 1 turn * 46 frames/turn) * n bytes/frame = 375 frames * n bytes/frame = (375 * n) bytes and n cells/turn * (7 turns * 47 bytes/cell + 1 turn * 46 bytes/cell) = n cells/turn * (8 turns * 46.875 bytes/cell) = (375 * n) bytes note that the short turn of the scheduler must still contain n cells, this means that we can not program a cell into the last frame of the long turn, because this last frame is not used during the short turn, and this cell would not be sent.
mt90500 47 using for an example the case of n=6, we would program the aal1 scheduler with 6 cell events over 46/47 frames: (7 turns * 47 frames/turn * 6 bytes/frame) + (1 turn * 46 frames/turn * 6 bytes/frame) = 375 frames * 6 bytes/frame = 2250 bytes and 6 cells/turn * (7 turns * 47 bytes/cell + 1 turn * 46 bytes/cell) = 6 cells/turn * (375 bytes/turn) = 2250 bytes to support aal1 nx64, one of the mt90500 schedulers can be set up with one turn of 46 and 7 turns of 47 (long end = 46, short end = 45, long/short = 7). we program n cells into the ?rst 46 frames of the scheduler, and we know that the 8 turns of the scheduler will take 375 frames, during which we will send n * 8 cells, containing n * 375 bytes of tdm data. a typical application of the mt90500 might have the last of the three schedulers set this way to support aal1 nx64. 4.3.1.3.4 other considerations the transmit circular buffer operation of the mt90500 is slightly more complex than the theoretical examples above. the mt90500 uses a four-frame buffer to optimize tdm data transfers, and this means that the transmit circular buffers are actually written four bytes at a time, every four frames. for this reason the schedulers in the mt90500 operate on the quad-frame by default. in addition, the long/short operation of the aal1 scheduler requires that an extra byte be held in the transmit circular buffer. finally, the number of frames between cells must be an integer. these extra considerations mean that in general a cell will not be transmitted when there are exactly m/n bytes in the transmit circular buffer, but at some point afterwards. this adds slightly to the transmission delay, but does not require attention on the part of the user, except in the programming of the circ. buff. pnt. ?eld of the transmit control structure (see below).
mt90500 48 4.3.2 tx_sar process figure 19 at the end of this section gives an overview of the processes explained below. a theoretical overview of scheduler operation is given above, in section 4.3.1.3. 4.3.2.1 transmit event schedulers as discussed in section 4.1.3, a 64-byte transmit circular buffer is maintained in external memory for each tdm channel whose data needs to be transmitted on the atm link. structures known as transmit event schedulers are used to tell the hardware when a cell needs to be assembled for transmission. the three transmit event schedulers all have similar properties and individual con?guration registers. each transmit scheduler is divided into a programmable number of frames. the circuitry operates to constrain each scheduler frame to last an average of 125 m s, which is the time required for 1 byte to be received / transmitted on each tdm channel. within each frame 8, 16, or 32 vc pointers can be programmed to transmit cells. when multiple schedulers are used simultaneously, one must assume that any frame in one scheduler can be superposed onto any frame in another scheduler. to limit cell delay variation, each frame (composed of events from one, two, or three schedulers) should contain no more than 45 vc pointers (or transmission events) for 155 mbps systems, and no more than 7 vc pointers for 25 mbps systems. for example, if three schedulers are programmed and each schedulers most-?lled frame contains respectively 22, 8, and 28 vc pointers, the worst case scenario is a frame with 58 cells, thus over the 45 vc pointers per frame limit for 155 mbps. this type of situation must be avoided to minimize the cell delay variation resulting from an unbalanced or temporarily overloaded transmit scheduler. the tx_sar will generate a fatal schedule error (see tx_sar status register at 2002h) if the schedulers fall behind in their scheduled cell transmission by 8 frames. this would be caused when more than 8 consecutive frames contain more than 7 (25 mbps) or 45 (155 mbps) vc pointers. the same error may also occur when the tx_sar is heavily loaded and other processes are using more bandwidth than they normally do. the rx_sar and utopia modules use the external memorys bandwidth unevenly over time, depending on the rate at which cells arrive. they can cause schedule errors in the tx_sar when the mt90500 is near its maximum load. this error is generated by the tx_sar when it is at least 8 frames (1 ms) late. to prevent cell delay variation, schedule errors, and tdm data unavailability, the software that con?gures the tx_sar should use an ef?cient algorithm to ?ll the event schedulers. events that send cells on the same vc must be evenly distributed in the event scheduler. the distance between two events associated with the same vc must be as constant as possible. for an 8-channel aal1-sdt type cell (with a pointer byte sent in cell #0 of each sequence), the distance between two events must be 46.975/8 ~ 5.86 frames. since this number must be an integer, the event spacing should be 6-6-6-5-6-6-6-5 frames. this regular transmission of cells is also important in limiting the cdv (cell delay variation) of the transmitted cells. each programmable event scheduler is composed of a base address, a short end, a long end, a long/ short ratio and a certain number of events per frame, as shown in figure 15. this information is set in the tx_sar registers located at addresses 2010h/2020h/2030h, 2012h/2022h/2032h, and 2014h/2024h/2034h. the key to supporting different cell types is to have a programmable short and long end for each scheduler. for aal1-sdt type cells, the scheduler ends at frame 45 for p-type cells (short end) and at frame 46 for non p- type cells (long end). the ratio between the long and short end can be programmed to either 1 (to generate p- type cells every even-numbered cell), 3 (to generate p-type cells every other even-numbered cell), or 7 (to generate p-type cells once in every 8-cell sequence). the psel ?eld in the transmit control structure (figure 16) must represent the long/short ratio in the event scheduler, except in the case of partially-?lled cells. for a vc which is to carry partially ?lled cells, the long/short ratio is set to 0. when the long/short ratio is equal to 0, the scheduler always counts to the long end before returning to frame 0. this mode is used for cbr-aal0, cbr-aal5, pointerless aal1 structured data transfer, and partially-?lled cell formats, since the number of cbr payload bytes in these cells is constant (regardless of the value of the psel ?eld). for a partially ?lled p-type cell (i.e. containing an aal1 pointer-byte) one less pad byte is inserted after the tdm data than for a partially ?lled cell without a pointer byte. the event scheduler can be truncated down to as few frames as necessary to support the desired partially-?lled cell length. on the other hand, the event scheduler can also be enlarged so that its length is an integer number which is a multiple of all the partial length formats that need to be supported. for example a scheduler of length 96 will support the following cell ?ll sizes: 1, 2, 3, 4, 6, 8, 12, 16, 24, 32, and 48. for speci?c examples regarding scheduler con?guration, please refer to the mt90500 programmers manual.
mt90500 49 when the mt90500 is used to transmit cbr-aal5 cells, additional register programming is required to properly initialize the tx_sar and the schedulers to send cells containing 32-bit crcs. regardless of which scheduler(s) is (are) to be used for transmission of the atm cells, the following initialization settings must be made: ? tx_sar end ratio register - scheduler a at 0x2014: set bits<7:6> = 01. ? tx_sar end ratio register - scheduler b at 0x2024: set bits<7:6> = 10 ? tx_sar end ratio register - scheduler c at 0x2034: set bits<7:6> = 11 21 0 2 3 4 15 frame 0 frame 1 frame 2 frame 3 frame 4 frame 5 frame 252 frame 253 frame 254 frame 255 vc pointer #1 vc pointer #2 vc pointer #3 vc pointer #4 vc pointer #29 vc pointer #30 vc pointer #31 vc pointer #32 t r tx_struct_pnt 0 15 12 b0_0000_0000 number of entries per frame given by entry<3:0> r = reserved (must be set to 0) t = entry type: 000 = inactive; 001 = non-cbr data; 010 = aal1/cbr-aal0; 111 = cbr-aal5; all other values = reserved frame 44 frame 45 frame 46 frame 47 +00 +3e programmable size (8, 16, or 32 entries per frame) 0 9 20 sbase (from 2010h,2020h,2030h) 0 0 0 0 0 0 0 0 0 pointer to start of event scheduler 0 4 20 txbase (from 2040h) 3 0 0 0 0 pointer to start of transmit control structure - see figure 16 16 15 tx_struct_pnt pointer to start of event scheduler pointer short end pointer long end minimum scheduler length - 1 frame maximum scheduler length - 256 frames sbase entry 2010h 2020h 2030h tesbaa tesbab tesbac <8:0> <20:0> <20:9> 12 11 8 figure 15 - transmit event scheduler
mt90500 50 4.3.2.2 transmit control structures within each frame within a transmit event scheduler 8, 16, or 32 vc pointers can be programmed. each entry represents a request to the hardware to generate a cell on that vc. an entry can be active or not, depending on the t bits located in the three lsbs of the entry word. an inactive entry is skipped. an active entry either tells the hardware to transmit the next non-cbr data cell held in the transmit data cell fifo in the external memory, (as explained in section 4.3.3) or to transmit a cbr cell characterized by the transmit control structure at the address pointed to by tx_struct_pnt. this latter process will be outlined in this section. once an active cbr vc pointer is found in the event scheduler, the tx_sar reads the transmit control structure (figure 16 for cbr-aal0 and aal1 type cells, figure 17 for cbr-aal5 type cells) and may either send a cell or not. the a bit in the transmit control structure indicates whether the structure is active (an inactive structure will never generate a cell). when opening a vc, this three step procedure must always be followed: ?rst, the software must write the transmit control structure into the memory and clear both the a and s bits in that structure; second, all events pointing to the transmit control structure must be written in the event scheduler; ?nally, the a bit must be set by the software. this procedure forces the hardware to ignore all events pointing to a transmit control structure until its a bit is set. when the a bit is set, all scheduler events for this vc immediately become active and the transmission process for this vc is enabled. please refer to the mt90500 programmers manual, for detailed information on setting up a vc for the tdm to atm transmit process. if the transmit control structure has never been updated by the hardware, the circ. buf. pnt ?eld must indicate how old (in terms of 125 m s tdm frames) the ?rst byte in the ?rst cell should be. for instance, if a cell contains 47 bytes, and the age of the ?rst byte to be sent is 46, the last byte to be sent in the cell will have an as gfc / vpi(11:8) 0 7 8 15 last entry first entry payload size current entry psel offset hec v v v v v v v v +00 +02 +04 +06 +08 +0a +0c +0e +10 +12 +14 +16 +58 +5a +5c +5e a seq special notes: first entry: indicates location of the first tx circular buffer address within the transmit control structure (lower bits are always 1000). note difference between first entry location in cbr-aal5 transmit control structure and aal1/cbr-aal0 transmit control structure. as: aal type. 00= cbr-aal5 (aal5 cells are a special case of aal0). psel: p-byte selection. 0000 for cbr-aal5. pti: lsb of field must be set to 1 to identify this as a cbr-aal5 type cell. circ. buf. pnt. vpi(7:0) vci(15:12) vci(11:0) pti minimum structure size - 18 bytes maximum structure size - 96 bytes r s 00 c1 figure 17 - transmit control structure format (cbr-aal5) tx circular buffer address (bits<20:6>) tx circular buffer address (bits<20:6>) 0000 0000 0000 0000 tx circular buffer address (bits<20:6>) tx circular buffer address (bits<20:6>) tx circular buffer address (bits<20:6>) tx circular buffer address (bits<20:6>) tx circular buffer address (bits<20:6>) tx circular buffer address (bits<20:6>) 0000 0000 0000 0000
mt90500 51 age of -1 (i.e. it hasnt arrived at the mt90500 yet). thus, in the case of a single channel aal1-sdt vc, the software must initialize the value of the circ. buf. pnt. to at least 47, ensuring that at least 47 bytes are available for cell assembly when the scheduler is ready to transmit an event. this will also ensure that the most recent 47 bytes of data are sent. a value greater than 56, however, is not recommended because the oldest data to be sent in a cell may be overwritten by the tdm module and replaced by new data. a value of 51 to 56 is recommended for any single channel aal1 or cbr-aal0 fully-?lled cell. when using hyper-channels or as gfc / vpi(11:8) 0 7 8 15 last entry first entry payload size current entry psel offset hec v v v v v v v v v v +00 +02 +04 +06 +08 +0a +0c +0e +10 +12 +14 +16 +f8 +fa +fc +fe a seq pointer to first tx circular buffer entry 0 7 8 20 0 first entry pointer to current tx circular buffer entry 0 7 8 20 0 current entry upper structure address pointer to last tx circular buffer entry 0 7 8 20 0 last entry upper structure address first entry: indicates location of the first tx circular buffer address within the transmit control structure (lower bits are always 110). a: structure active bit. 0 = inactive; 1 = active. last entry: indicates where last tx circular buffer address is located within the transmit control structure. hec: hec value (optional). as: aal type. 00= cbr-aal0/aal5; 01=reserved; 10=aal1; 11=aal1- srts payload size: indicates the number of payload bytes within an atm cell. full cell = 2fh. partially-filled cells = 03h to 2eh. current entry: indicates location of the current transmit circular buffer. must be initialized to first entry value and is incremented by hardware. seq: indicates aal1 sequence number. possible sequence values are 000 to 111. must be initialized by software to 000. circ. buf. pnt: this field must be initialized by software to initial offset required between tx_sar read pointer and tdm circular buffer write pointer. offset : offset value between the tdm circular buffer write pointer and the tx_sar read pointer is stored in this field. should be set to initial value of 0. r: reserved (set to 0). s: structure initialized. 0 = uninitialized; 1 = initialized. must be set as 0 by s/ w. psel: p-byte selection. 0 for pointerless aal1 structured data transfer and cbr-aal0; 8 for standardized sdt (see text for more details). gfc: cell header gfc field (uni). vpi: cell header vpi field. vci: cell header vci field. pti: cell header pti field. lsb of field, when set to 1, indicates oam-type cell. c1: cell header clp bit. v: tx circular buffer valid bit. 0 = invalid entry; 1 = valid tx circular buffer address. tx circular buffer address: this is the upper part of the address that points to a transmit circular buffer (bits 20:6). the buffer must be located relative to the tx circular buffer base address (txcbbase) set in register 6044h. circ. buf. pnt. vpi(7:0) vci(15:12) vci(11:0) pti minimum structure size - 14 bytes maximum structure size - 256 bytes r s 00 c1 0 4 20 3 0 0 0 0 pointer to start of transmit control structure 16 15 tx struct pointer (see figure 15) upper structure address note: upper structure address is obtained from the upper 13 bits (i.e. bits<20:8>) of the pointer to start of transmit control structure. figure 16 - transmit control structure format (aal1 & cbr-aal0) tx circular buffer address (bits<20:6>) tx circular buffer address (bits<20:6>) tx circular buffer address (bits<20:6>) tx circular buffer address (bits<20:6>) tx circular buffer address (bits<20:6>) tx circular buffer address (bits<20:6>) tx circular buffer address (bits<20:6>) tx circular buffer address (bits<20:6>) tx circular buffer address (bits<20:6>) tx circular buffer address (bits<20:6>) note: transmit control structures must start on 16-byte boundaries and cannot overlap 256-byte boundaries. txbase (from 2040)
mt90500 52 partially-?lled cells, much lower values should be written in this ?eld, thus reducing transmission delay. the following equations (used to calculate the initial circ. buf. pnt. to be written by the software) are valid for most cell types: aal1 sdt-type cells: circ. buf. pointer = roundup ((max. # of payload bytes per cell / # of channels per vc) * roundup (# of channels per vc / min. # of payload bytes per cell * 4)) + 5 all other cells: circ. buf. pointer = roundup ((max. # of payload bytes per cell / # of channels per vc) * roundup (# of channels per vc / min. # of payload bytes per cell * 4)) + 4 the offset ?eld is used by internal hardware to verify the offset between the tdm circular buffer write pointer and the tx_sar read pointer (which is stored in circ. buf. pnt. in the transmit control structure, once the structure becomes active). offset should be initialized to 00h. all transmit control structures must begin on 16-byte boundaries, and may not overlap 256-byte boundaries. any transmit control structure that overlaps a 256-byte boundary will cause unpredictable sar behaviour. the first entry, current entry, and last entry ?elds are pointers that must be set relative to the beginning of the particular transmit control structure. the first entry ?eld represents the location of the ?rst tx circular buffer address within a transmit control structure. this 7-bit ?eld represents the 8 lsbs of the actual entry location divided by two (shifted right by one). when the transmit control structure represents cbr-aal0 or aal1 type data, the lower three bits of the first entry will always be 110 since the ?rst entry is always 12 bytes away from the start of the transmit control structure. when transmitting cbr-aal5 type cells, the lower four bits of the first entry will always be 1000 because the ?rst tx circular buffer address is located 16 bytes away from the start of the transmit control structure. the current entry and last entry ?elds are programmed similarly, with current entry bearing the same address as first entry when the structure is initialized by software. the programming of the first entry and last entry ?elds for two examples can be seen below in figure 18. note that the transmit control structure is not active until the a bit in the ?rst byte of the structure is set high. the cell header portion of the transmit control structure is passed directly to the utopia bus without any modi?cations. typically, the phy device will calculate the hec and over-write the hec ?eld in the transmit control structure. however, in the case where the phy device does not calculate the hec ?eld, the hec byte may be calculated by the cpu, and written into the hec ?eld of the transmit control structure. the as ?eld indicates to the tx_sar if the vc is a cbr-aal0/aal5, aal1-srts, or aal1 vc. note that only one transmit control structure can be programmed with the aal1-srts ?ag. the srts only changes relative to one vc since it can only be synchronized to one vc. the payload-size ?eld in the transmit control structure indicates the number of tdm bytes carried in an atm cell. for a fully-loaded cell of aal1 or cbr-aal0, the payload-size ?eld must be set to a value of 2fh (decimal 47) which represents a full payload for cbr-aal0 (48 tdm bytes), pointerless aal1 structured data transfer (47 tdm bytes plus 1 aal1 byte), and aal1-sdt (47 tdm bytes plus 1 aal1 byte, or 46 tdm bytes plus 1 aal1 byte plus 1 pointer byte). for a fully-loaded cell of cbr-aal5, the payload-size ?eld must be set to a value of 27h (decimal 39) which represents a full payload for cbr-aal5 (40 tdm bytes). for partially-?lled cells, the payload-size ?eld may be set to a value ranging from 03h to 2eh. note that these values represent different numbers of payload bytes, depending on the type of data structuring that is being used. for example, to represent a ?ll of 32 tdm bytes in each cbr-aal0 or cbr-aal5 cell, the user should set a payload-size of 1fh. however, in order to ensure that each aal1 cell (sdt or pointerless structured data transfer format) contains 32 tdm bytes, the payload-size must be set to 20h. similarly, while a payload-size of 7h indicates that the transmitted cbr-aal0 or cbr-aal5 cells contain 8 bytes of tdm data a payload-size of 8h is required to ensure a ?ll of 8 tdm bytes in each cell transmitted using aal1-sdt or pointerless aal1 structured data transfer. in general, the payload-size ?eld should be set to the expected number of tdm bytes when transmitting aal1-type cells, and it should be set to one less than the expected number of tdm bytes when transmitting cbr-aal0 and cbr-aal5 cells. as well, it should be noted that 2eh (decimal 46) is an illegal value for aal1-sdt. the psel nibble is used to denote the cell(s) within an 8-cell sequence in which the pointer byte (p-byte) is to be sent. when using pointerless aal1 structured data transfer, no pointer cells are ever sent, and the psel nibble must be initialized to 0h. with sdt, pointers may be sent in cells 0, 2, 4, or 6 of a sequence. the mt90500 can support both standardized and proprietary sdt formats. in order to meet itu-t i.363.1, a structure (i.e. a speci?c vc) must be composed of no more than 96 channels, and the p-byte must be sent in the ?rst (i.e. sequence number = 0) cell of each 8-cell cycle. thus the psel ?eld must be set to 1000 (the
mt90500 53 psel bits are one-hot bits which represent cells with sequence numbers 0, 2, 4, and 6, respectively - see table 10 below for an explanation of bit operation). the mt90500 also supports proprietary pointer transmissions in which a p-byte is sent every 4 cells (psel = a hex) or every other cell (psel = f hex). using these proprietary methods, up to 122 channels can be sent on a particular vc, but this is only possible if the receiving chip can handle the extra p-bytes during a cycle. each tx circular buffer address appended to the end of the structure points to a 64-byte circular buffer in external memory. table 10 - effect of psel field on p-byte generation sequence # 0 sequence # 2 sequence # 4 sequence #6 applicable standards 0000 no pointers are sent. ansi and itu-t - aal0, aal5, pointerless aal1 structured data transfer, and partially- filled cells 1000 pointer sent. - - - ansi and itu-t - aal1-sdt 1010 pointer sent - pointer sent - ansi - aal1-sdt 1111 pointer sent pointer sent pointer sent pointer sent ansi - aal1- sdt 8 15 0 7 first entry field 1 0 0 0 1 1 0 last entry field 1 0 0 1 0 0 0 20180 gfc / vpi(11:8) last entry first entry payload size current entry psel offset hec tx circular buffer address v 0 a as seq circ. buf. pnt. vpi(7:0) vci(15:12) vci(11:0) pti r s 00 c1 20182 20184 20186 20188 2018a 2018c tx circular buffer address v 2018e first entry location = 2018c tx circular buffer address v 20190 last entry location = 20190 a a figure 18 - a: sample three-channel transmit control structure (aal1/cbr-aal0) 0 0 8 15 0 7 first entry field 1 0 0 1 0 0 0 last entry field 1 0 0 1 0 0 0 20180 gfc / vpi(11:8) last entry first entry payload size current entry psel offset hec 0 a as seq circ. buf. pnt. vpi(7:0) vci(15:12) vci(11:0) pti r s 00 c1 20182 20184 20186 20188 2018a 2018c 2018e first entry location = 20190 tx circular buffer address v 20190 last entry location = 20190 a a 0 0 figure 18 - b: sample one-channel transmit control structure (cbr-aal5) 0000 0000 0000 0000 0000 0000 0000 0000
mt90500 54 tdm bus interface logic tx aal1 sar tdm bus 16 lines 1024 x 64kbps (max.) tx utopia mux main utopia interface secondary utopia interface from external sar to external phy tdm clock logic clock signals mt90500 external synchronous sram tdm module internal tdm frame buffer utopia module local tdm bus 32 x 64 kbps in/ 32 x 64 kbps out tx circular buffers - one for each tdm channel to be transmitted transmit control structures - one for each vc transmit event scheduler - one for each type of aal data (3 schedulers possible) ? ? ? ? ? ? transmit circular buffer control structure directs tdm data to circular buffers dictate which circular buffer data to be sent on each vc controls scheduling of transmission of vcs within frames primary cell queue secondary cell queue a b c figure 19 - overview of cbr data transmission process
mt90500 55 4.3.3 non-cbr data cell transmission capability the tx_sar also has the ability to transmit cpu-written non-cbr data cells directly from a user-de?ned fifo in external memory (the transmit data cell fifo) to the utopia module. non-cbr data cells include oam cells, other signalling cells, and aal5 cells containing cpu data. once the cpu writes the complete cell into the transmit data cell fifo, the utopia module then treats these non-cbr data cells the same as the normal cbr cells. all 53 bytes of the non-cbr data cells are written by the microprocessor into the fifo in 64-byte long structures located on 64-byte boundaries (see figure 21). there are 16, 32, 64 or 128 of these structures contained in the circular fifo, mapped in the external memory at the address determined by the transmit data cell fifo base address register (register 2050h). this fifo must not overlap an 8-kbyte boundary. if the fifo does overlap an 8k boundary, some or all of the non-cbr cells sent by the tx_sar will be corrupted. there are two ways to control transmission of non-cbr data cells: by scheduler, or by autodata. the scheduler method requires mapping data cell events into one of the transmission schedulers being used. this is done by writing 001 in the entry type section of the vc pointer entry, as shown in figure 20. in this case, when the scheduler hits the frame within which this entry is contained, it will read the next valid data cell from the transmit data cell fifo and transmit it. because non-cbr cell transmission does not require the use of transmit control structures, the tx_struct_pnt ?eld in the vc pointer is not used and thus its value is irrelevant. note that using the scheduler(s) to control non-cbr data transmission results in regularly spaced non-cbr data cells, as speci?ed in the scheduler entries. the other possibility for controlling transmission of non-cbr data cells is by using the autodata bit in the tx_sar control register at 2000h. while that bit is high, once the tx_sar has completed its assigned cells for a certain quad frame (or frame) and is waiting for its next pulse (i.e. the tx_sar is idle), the mt90500 will automatically transmit data cells, provided that data cells are available in the transmit data cell fifo. this process will end as soon as the next pulse is detected ( note: the non-cbr cell being treated at that time will be completed before the tx_sar returns to cbr cell assembly). both these cases require the microprocessor to write the full non-cbr data cell into the transmit data cell fifo, and then to write the new (incremented) value of the transmit data cell fifo write pointer (address 2052h). non-cbr data cells will only be sent if the transmit data cell fifo write pointer and the transmit data cell fifo read pointer (address 2054h) indicate that there are valid cells contained in the fifo. when the pointers are not equal, the tx_sar goes to the appropriate address indicated by the transmit data cell fifo base address register (address 2050h) and reads the non-cbr data cell. note that although the fifo read pointer will be automatically adjusted to ?t the transmit data cell fifo size (for example, if the fifo size is 32 cells, when the read pointer is 31 and a cell is read, it will wrap around to 0), that is not true of the write pointer. therefore, if the fifo write pointer is set to 128, non-cbr cells will always be considered valid. 0 2 3 4 15 0 xxxx xxxx xxxx 001 vc pointer 2 3 4 15 r tx_struct_pnt t r = reserved (must be set to 0) t = entry type (000 = inactive; 001 = non-cbr data; 010 = aal1/cbr-aal0; 111 = cbr-aal5; all others: reserved) 0 figure 20 - vc pointer for scheduler-controlled non-cbr data cell
mt90500 56 vpi(7:0) gfc or vpi(11:8) 0 7 8 15 data byte #1 reserved vci(11:0) +00 +02 +04 +06 +08 +0a +0c +0e +10 +3e reserved hec byte reserved data byte #0 data byte #3 data byte #2 data byte #5 data byte #4 data byte #7 data byte #6 data byte #9 data byte #8 data byte #43 data byte #42 data byte #45 data byte #44 data byte #47 data byte #46 reserved reserved reserved reserved reserved reserved reserved reserved +38 +3a +3c +32 +34 +36 pti, etc. vci(15:12) figure 21 - transmit non-cbr data cell structure format
mt90500 57 4.4 the rx_sar module figure 30 at the end of this section gives an overview of the processes explained below. 4.4.1 rx_sar overview the rx_sar block performs cell identi?cation and reassembly functions on data moving from the primary utopia port (refer to section 4.5) toward the tdm interface. the rx_sar module receives cells from the utopia module, which has the capability of identifying cells as either cbr cells or non-cbr data cells. when non-cbr data cells are received by the utopia module, they are stored in a multi-cell circular buffer located in external memory. when cbr cells are detected (aal1, cbr-aal5 or cbr-aal0), they are processed and the payload is extracted and stored in time slot-related circular buffers, the size of which can be individually programmed by software on a per-vc basis. the rx_sar block supports aal1-sdt, pointerless aal1 structured data transfer (for itu i.363.1 voiceband signal transport) and aal0 cell formats. cbr-aal5 cells are treated as partially-?lled aal0. single or multiple (up to 122) tdm channels are supported per virtual circuit (speci?c vpi/vci). on the receive side, the mt90500 rx_sar block has the ability to receive and process up to 1024 virtual circuits simultaneously (and up to 1024 tdm channels at 64 kbps), resulting in a total of about 74 mbps of bandwidth on the receive side. if 1024 tdm channels are used for full-duplex connections such as phone calls, the bandwidth will be ~74 mbps per direction. the amount of external memory required for the handling of receive vcs is variable and is de?ned by the user. the external memory requirements to support the rx_sar are scalable and depend mainly on the number of tdm channels that need to be received on the atm link and the size of the receive circular buffer required to compensate for latency and cdv (cell delay variation). as an example, the reception of 1024 simultaneous virtual circuits, each representing a 64 kbps channel, each with a 128 ms buffer, requires external memory capacity exceeding 1024 kbytes (sram). the rx_sar module has no interface to the external pins. it has internal connections to the external memory controller, the utopia module, and the microprocessor interface. it also receives synchronization signals from the tdm module. no fatal errors can be generated by the rx_sar. most of the registers associated with it are targeted at network statistics and error monitoring. 4.4.2 rx_sar process as explained in section 4.5, detailing the operation of the utopia module, cells received over the atm link that are intended for the rx_sar are tagged and forwarded to the rx_sar module. for the traf?c tagged as cbr, the rx_sar then uses control information in the rx_sar control structures to extract the payload data from the received cell and store it into tdm channel rx circular buffers located in external memory. for the traf?c tagged as non-cbr data, the rx_sar simply stores the whole cell, which is considered to be a raw aal0 cell, in a circular fifo located at the address speci?ed by the receive data cell fifo base address register (4020h). this will be explained further in section 4.5.4. in addition, timing reference cells (which may carry cbr traf?c or non-cbr data) can also be received on the atm side of the mt90500. as outlined more fully in section 4.5.3, the reception of these cells results in the generation of timing pulses used in adaptive clock recovery. for each vc assigned to cbr traf?c in reception, an rx_sar control structure has to be set up and maintained in external memory, as explained below.
mt90500 58 4.4.2.1 rx_sar control structures the rx_sar control structure is quite similar to the transmit control structure shown in figure 16, but it has added cell delay variation control ?elds (as seen in figure 22). the first entry, current entry, last entry, as, s, payload size, v, and rx circular buffer base address ?elds all have the same properties as in the tx_sar. bs 0 7 8 15 last entry first entry figure 22 - rx_sar control structure average lead payload size current entry aal1 byte reserved rx_sar write pointer minimum lead maximum lead rx circular buffer base address (bits<20:6>) v v v v v v v v v v +00 +02 +04 +06 +08 +0a +0c +0e +10 +12 +14 +16 +f8 +fa +fc +fe s 0 as 0 pointer to first rx circular buffer entry 0 7 8 20 0 first entry upper struct address pointer to current rx circular buffer entry 0 7 8 20 0 current entry upper struct address pointer to last rx circular buffer entry 0 7 8 20 0 last entry upper struct address first entry: indicates location of the first rx circular buffer base address within the rx_sar control structure. last entry: indicates where the last rx circular buffer base address is located within the rx_sar control structure. minimum lead: indicates the minimum number of bytes that must always be valid in the rx circular buffer (to get the number of bytes, multiply minimum lead by four). usually initialized to 01h. maximum lead: indicates the maximum number of bytes that may be valid in the rx circular buffer (to get the number of bytes, multiply maximum lead by four). average lead: indicates the average number of bytes that are valid in the rx circular buffer (to get the number of bytes, multiply average lead by four). equal to (minimum lead + maximum lead) / 2. as: aal type. 00= cbr-aal0 & cbr-aal5; 01=reserved; 10=aal1; 11=aal1-srts payload size: indicates the number of payload bytes within an atm cell. full cell = 2fh (48 bytes). partially-filled cells = 03h to 2eh. current entry: indicates location of the current receive circular buffer. must be initialized to first entry value and is incremented by hardware (or realigned with arrival of pointer byte). aal1 byte: used by hardware to check for cell loss / misinser- tion. should be initialized to 00h. s: structure initialized. 0 = uninitialized; 1 = initialized. must be set as 0 by s/w. bs: circular buffer size. 000 = 64 bytes; 001 = 128 bytes; 010 = 256 bytes; 011 = 512 bytes; 100 = 1024 bytes; other = reserved. rx_sar write pointer: when s bit is 0, uninitialized; when s bit is 1, indicates which byte in the rx circular buffer the hard- ware will write first with the data in the next cell. v: receive circular buffer valid bit. 0 = not valid; 1 = valid (write received cell data to a circular buffer). rx circular buffer base address: this is the upper part (bits 20:6) of the address that points to a receive circular buffer. note : rx circular buffers must be located on boundaries corre- sponding to the size of the buffer (see figure 7 on page 37 for clari?cation). reserved: set to all zeroes. reserved minimum structure size - 14 bytes maximum structure size - 256 bytes 20 18 17 0 3 4 rx structure address (set by software) pointer to start of rx_sar control structure rxbase (from 4000) 0 0 0 0 0 note: upper struct address is obtained from the upper 13 bits (i.e. bits<20:8>) of the pointer to start of rx_sar control structure. note: rx_sar control structures must start on 16-byte boundaries and cannot overlap 256-byte boundaries. rx circular buffer base address (bits<20:6>) rx circular buffer base address (bits<20:6>) rx circular buffer base address (bits<20:6>) rx circular buffer base address (bits<20:6>) rx circular buffer base address (bits<20:6>) rx circular buffer base address (bits<20:6>) rx circular buffer base address (bits<20:6>) rx circular buffer base address (bits<20:6>) rx circular buffer base address (bits<20:6>)
mt90500 59 three cell delay variation control ?elds must be initialized by the software: the minimum lead, maximum lead and average lead. each of these ?elds is concatenated with 00 (i.e. multiplied by 4) to have a range from 0 to 1020. before disassembling any cell, the rx_sar veri?es its write pointers validity with respect to the maximum and minimum lead ?elds, as discussed in section 4.4.2.2. the aal1 byte is used by hardware to check the cell sequence number and therefore provide cell loss / misinsertion detection. before opening a vc, the user should write 00h into this ?eld and then leave it for hardware control. the s bit (structure un-initialized) serves to indicate that the structure has not been run yet. when the ?rst cell of a vcc arrives at the mt90500, the rx_sar control structure is called by the lookup table for the ?rst time, and the 's' bit is '0' as set by software. when the hardware loads the rx_sar control structure from memory, and sees that bit-15 in the 6th word is '0' (s is 0), this ?rst cell is written starting at the location of the average lead pointer, which automatically sets up the buffer with average-lead of cdv tolerance. the bs ?eld indicates the size of the receive circular buffers. the valid size ranges from 64 to 1024 bytes and depends upon the amount of available memory and the cell delay variation (cdv) in the network. note that all channels arriving on the same vc must have the same cdv and therefore their rx circular buffers will all be the same size. the rx_sar write pointer is initialized to zero by software and used only by the hardware. unlike the transmit control structures, there is no difference in the con?guration of the rx_sar control struc- tures for the various cell types. in fact, the only thing which differentiates the control structures for different aals is the as ?eld. in particular, this ?eld is set to 00 for cbr-aal0 and cbr-aal5 cells (because cbr- aal5 is really just a special case of cbr-aal0), or 10 for aal1. aal1 cells which are carrying srts information are identified by an as setting of 11. as with the transmit control structures, all rx_sar control structures must start on 16-byte boundaries and must never cross 256-byte boundaries. 4.4.2.2 rx_sar error counter and interrupt sources the rx_sar has three 16-bit error counters, and three error structure id registers for error monitoring. when receiving a cell, any of the following errors can be detected: a write overrun error, a write underrun error, an aal1 byte parity error, an aal1 crc error, a sequence number error, a p-byte parity error, or a p-byte out of range error. a counter and id register are used to monitor each of the two write slip-type errors (3022h and 3020h for underrun events; 3032h and 3030h for overrun events). the other ?ve types of errors share common counter (3012h) and event id (3010h) registers. five bits in the rx_sar control register (3000h) allow the control software to choose which error events affect the count and id registers. if more than one error count enable is active, the counter will add all occurrences of the various errors. the id register points to the rx_sar control structure which experienced the last recorded error. all of the errors should be self- explanatory, except for the p-byte out of range error. this error occurs when the p-bytes value implies that a hyper-channel contains more channels than indicated by the rx_sar control structure. note that received cells with aal1 errors (e.g. sequence numbers, aal1-byte parity, aal1-byte crc, p-byte parity and p-byte crc) are not discarded. the dropping of such cells is optional in the af-vtoa-0078 ces- is v2.0 speci?cation. the cell contents are passed to the aal1 reassembly process on the basis that corruption of the aal1-byte may or may not imply corruption of the tdm contents, and that tdm channels are generally relatively tolerant of noise, and that using these cells will help to maintain timing.
mt90500 60 4.4.2.3 receive overruns and underruns the first entry and last entry ?elds in the rx_sar control structure point to the ?rst and last rx circular buffer base address pointers in the rx_sar control structure. the minimum lead, maximum lead, and average lead entries de?ne the window within the circular buffer within which cell data can be received without generating an underrun or overrun condition. this window is de?ned relative to the tdm circular buffer read pointer, as described in figure 23. whenever data from a newly received cell is to be written to the receive circular buffers, the location of the rx_sar write pointer is checked against the minimum and maximum lead pointers. when a new cell is received, the hardware checks for the location of the rx_sar write pointer, which indicates where the new cell should be written within the associated receive circular buffer(s). the valid bytes shown in the ?gure above indicate bytes which have been written by the rx_sar and have yet to be read by the external memory to tdm data output process. consequently, invalid bytes represent those that have already been read or, in the case of start-up, have never been written. if the pointer falls within the window de?ned by the min. lead and max. lead parameters, the new data is written immediately following the old data. if the rx_sar write pointer falls after the maximum lead pointer, an overrun condition is detected, and the new data is written starting at the location of the average lead pointer. (some addresses containing previously received, unread data bytes are overwritten.) if the rx_sar write pointer falls before of the minimum lead pointer, an underrun condition is detected, and the new data is written starting at the location of the average lead pointer. (some addresses containing already-read data bytes are skipped and left unwritten.) figure 23 depicts the write pointer to read pointer comparison that occurs at cell receive time. the external memory to tdm data output process (section 4.1.4) has its own tdm read underrun error indication (see register 6000h) which works in parallel to the mechanism described above. the ninth bit of the external memory byte is not used for parity, but is used to indicate whether each tdm byte has been previously transferred to the tdm bus. when the external memory to tdm data output process reads a byte which has already been transferred (has the ninth bit set), an underrun condition is ?agged, if enabled by that tdm channels entry in the external memory to internal memory control structure. since this tdm read underrun error functions as each byte is read (and not just when a cell arrives, as the rx_sar errors do) it is useful to indicate dropped vcs (no cells), and excessive cdv (late cells). data bytes which have been read out to the tdm bus by the external memory to tdm data output process are handled according to the programming of the external memory to internal memory control structure. depending on the value of the write-back disable bit for each individual tdm channel, bytes read out to the tdm bus will either be replaced by silence (ffh) or left unchanged. this has the effect that in the event of an underrun, either silence (ffh) will be read out of the skipped area, or the old data in the skipped area will be repeated on the tdm bus. receive buffer tdm circ. buffer read pointer min. lead max. lead figure 23 - overrun and underrun situations write pointer receive buffer max. lead write pointer normal overrun underrun receive buffer avg. lead invalid byte valid byte valid byte valid byte valid byte valid byte valid byte invalid byte invalid byte invalid byte invalid byte invalid byte invalid byte invalid byte invalid byte valid byte valid byte valid byte valid byte valid byte valid byte valid byte valid byte valid byte valid byte valid byte valid byte invalid byte avg. lead (old) write pointer (new) invalid byte valid byte valid byte valid byte invalid byte invalid byte invalid byte invalid byte invalid byte invalid byte invalid byte invalid byte invalid byte invalid byte min. lead write pointer (new) write pointer (old) min. lead max. lead rx_sar rx_sar rx_sar rx_sar rx_sar tdm circ. buffer read pointer tdm circ. buffer read pointer
mt90500 61 registers 3022h and 3032h are used to maintain statistics on the occurrence of rx_sar underrun and overrun conditions. the last vc where an underrun or overrun condition was detected is also recorded in the event id registers 3020h and 3030h. note: care must be taken when assigning the maximum lead value for small circular buffers: when the maximum lead is too far from the tdm read pointer, the reception of a cell could write new data over the data being read by the tdm module. this error can occur if {(maximum lead) + (# of bytes in cell)} > (circular buffer size). 4.4.2.4 lost cell handling in the event of a lost cell, the mt90500 maintains bit count integrity through buffer-?ll level monitoring, rather than through sequence number processing (itu-t rec. i.363.1 terminology). sequence numbers are however monitored, and errors are reported (registers 3000h and 3002h). in the event of an under?ow (due to lost cells or excessive cdv) the buffers are reset to avg. lead for all tdm channels carried by a particular vc. in the event of a single cell loss: ? rx_sar write underrun will detect underrun if the cdv tolerance is depleted (3002h); ? tdm read underrun will detect underrun if rx circular buffer is depleted (6002h); ? sequence number error will be detected (3002h). in the event of loss of multiple consecutive cells: ? rx_sar may detect write underrun or write overrun (dependent on number of cells lost, and rx circular buffer size); ? tdm read underrun will detect underrun if rx circular buffer is depleted; ? sequence number error will be detected. in the event a vc gets disconnected: ? tdm read underrun will detect underrun (once rx circular buffer is depleted). note that the operation of the tdm read underrun error bit requires that the tdm read underrun detection enable bit in the external to internal memory control structure be asserted (for the particular tdm channel in question) and 9-bit (parity) memory is used (36-bit rather than 32 bit external memory). in the event of a cell loss not large enough to trigger one of the underrun alarms, the tdm data is read as normal from the rx circular buffer. this will jump the data from the lost cell, similar to a frame slip in tdm switches. in the event of a tdm read underrun error, the tdm output depends on the state of the external memory to internal memory control structure write-back disable bit, as explained in section 4.4.2.2. if enough cells are lost on a particular vc, causing the tdm circular buffer read pointer to advance far enough to wrap around, it is possible for the rx_sar to mistakenly declare an overrun when a cell ?nally arrives. using a larger circular buffer ram allocation makes this less likely to occur, since the ram is re-used at greater intervals. (the delay is not increased, as delay is controlled by maximum lead and average lead, not by the ram allocation.) in any event, the tdm read underrun will correctly identify an underrun, even in situations of large numbers of lost cells.
mt90500 62 4.5 utopia module on the atm transmit side, the mt90500 multiplexes atm cells generated by the internal tx_sar module with atm cells coming from the secondary utopia port. cells coming from the secondary utopia port may be generated by the optional external sar device (e.g. aal5 sar) or another mt90500 device (see figure 63, utopia bus interconnections for two mt90500s and an aal5 sar, on page 139 for an application example). 4.5.1 utopia overview the utopia module is used to daisy chain one or several sar devices in order to use a single phy device, as seen below in figure 24. in the transmit direction, the secondary utopia port of the mt90500 emulates a phy, receiving cells from other sar devices on the bus. the mt90500 then forwards these cells to the actual phy using the primary utopia bus. the transmit portion of the utopia module multiplexes the cell traf?c from the secondary utopia bus with the cell traf?c from the mt90500s tx_sar. a small internal fifo is used to buffer up to four secondary utopia bus cells) and four tx_sar cells. the tx_sar and secondary utopia bus can have the same transmit priority, or the priority can be given to the tx_sar (this is determined by the round-robin priority bit in the utopia control register at 4000h). no overruns are possible in the tx part of the utopia interface since ?ow control (utopia bus handshaking) is used. on the receive side, the mt90500 passively taps the receive utopia bus. since the receive utopia bus is multi-drop, cells may be received by more than one device. this can be used for redundant transfer of data or timing. cells can be received at the maximum transfer rate of the bus (up to 25 mhz). when a cell is received, its header is analyzed: the cell is either ignored, or stored in the primary receive fifo. (ignored cells are assumed to be destined for another device on the receive utopia bus.) the primary receive fifo is internal to the mt90500, and can contain 32 cells. if the internal primary receive fifo is full, the received cell is discarded, so it is important to use a master clock rate (mclk) fast enough for the application. further details on the cell reception process are given in section 4.5.3. all cell transfers on both utopia buses are performed using cell-level handshaking. see af-phy-0017 for more information regarding utopia standards. for details on chaining utopia devices, see section 7, applications of this datasheet. details on con?guring the ptxclk pin are in the main control register, on page 84. rx rx rx rx tx tx tx tx abr sar device phy device atm network figure 24 - mt90500 daisy chain example mt90500 device mt90500 device
mt90500 63 . 4.5.2 cell transmission and mux process the general block diagram of the mux and internal fifo sub-module is shown above. the mux sub-modules operation is relatively straight-forward. it multiplexes onto the primary transmit utopia port cells generated by the tx_sar with cells received from the optional external sar device. a number of register bits found at address 4000h control the operation of the sub-module: a general enable (rxena); an external sar interface enable (stxena); and a mux arbitration method (rrp, which gives priority to the tx_sar or allocates priority in round-robin fashion). 4.5.3 receive cell selection process the purpose of the receive cell selection process is to determine the routing of received atm cells, which can include oam cells, timing reference cells, cbr cells destined for the rx_sar, and non-cbr data cells which will be routed to the receive data cell fifo. the steps involved in the receive cell selection process are detailed below and are outlined in the ?ow chart in figure 26. the receive cell selection process is as follows: a) the most signi?cant bit of the pti ?eld in the cell header is examined to determine if the cell is an oam cell. if the received cell is an oam cell, it is either sent to the 32-cell (2048-byte) internal primary receive fifo, or discarded as determined by the oam routing select bit, oamsel, in the utopia control register at 4000h. oam cells that are sent to this internal fifo are then treated as non-cbr data cells and are eventually sent to the receive data cell fifo in external memory; see step (e). if the cell is not an oam cell, step (b) is taken. b) non-oam cells are then passed through the mt90500s timing ?lter mechanism. the vpi and vci values of the incoming cell are compared to the values found within the vpi timing register (401ah) and the vci timing register (401ch). if the vc of the received cell matches the timing registers, a timing pulse is sent to the clock recovery module, along with the aal1 byte of the cell header (this process is explained in detail in section 4.6.1, adaptive clock recovery sub-module). regardless of whether the cell matches the timing ?lter or not, the cell is sent to step (c) for further processing. fifo tx mux rx fifo & vc search engine device boundary fifo fifo from to/from microprocessor i/f tx_sar to / from tdm module figure 25 - mux and internal fifo sub-module block diagram to/from memory controller to rx_sar secondary utopia port primary utopia port
mt90500 64 c) the cells vpi ?eld (8 bits) is examined. a bit by bit comparison of the vpi is performed using the contents of both the vpi match register (4012h) and the vpi mask register (4014h). if a bit value in the vpi mask register is 0, no comparison is performed on the corresponding bit in the vpi match register (and the bit is automatically accepted). if a bit value in the vpi mask register is 1, the comparison result will only be true if the received vpi bit and the corresponding vpi match register bit are identical. the cell will only be processed further (i.e. proceed to step (d)) if each of the 8 bit comparisons produces true results. otherwise, the cell will be discarded. d) the cells vci ?eld (16 bits) is then examined. a bit by bit comparison of the vci is performed using the contents of both the vci match register (4016h) and the vci mask register (4018h). if a bit value in the vci mask register is 0, no comparison is performed on the corresponding bit in the vci match register. if a bit value in the vci mask register is 1, the comparison result will only be true if the received vci bit and the corresponding vci match register bit match. step (e) will only be executed if each and every one of the 16 bit comparisons produces true results. otherwise, the cell will be discarded. note: the vpi/ vci match and mask ?lter serves two important purposes. it can eliminate non-unique look-up- table entries (important as the look-up-table space is smaller than the entire vpi/vci space of 16m addresses). it can also reduce the number of unnecessary look-up-table accesses (and unnecessary memory-access bandwidth) by eliminating cells with vpi/vci not destined for the mt90500. the user is advised to set the vpi/ vci match and mask ?lter as narrowly as practical for the application. e) any cell which passes through both the vpi and vci match ?ltering will be placed in the 32-cell fifo of the utopia module. cells are then read out by another internal process. as mentioned in step (a) above, oam cells which are located in the primary receive queue are automatically placed into the receive data cell fifo. on the other hand, non-oam cells are passed to the lookup engine of the utopia module, as explained in step (f). (f) within the look-up engine, the n least signi?cant bits of the vci and the m least signi?cant bits of the vpi are concatenated together to form a 15-bit word. if m + n is smaller than 15, the missing most signi?cant bits of the 15-bit word are zeroed. two least signi?cant zeroes are appended automatically (by h/w) to this word to form a 17-bit pointer aligned on a double-word boundary. note: this is explained more fully in the register description for the vpi/vci concatenation register at address 4010h. this pointer is added to the contents of the look-up table base address register at address 401eh to form a memory pointer into the vc look-up table, which is composed of 32-bit entries. the look-up engine then examines the t bits of each look-up table entry. these bits indicate the type of information being carried by a particular cell and therefore determine the ?nal destination of the cell: ? 00 indicates an unde?ned cell type. in this case, the cell is either discarded or treated as a non- cbr data cell which is placed in the receive data cell fifo. this ?nal cell routing is dependent on the setting of the uksel (unknown routing select) bit in the utopia control register at 4000h. ? 01 represents a non-cbr data cell. in this case, the cell is stored in a 64-byte long structure within the receive data cell fifo (see figure 29). ? 10 indicates a cbr cell. in this case, the rx structure address in the look-up table, (figure 27) is used to access the rx_sar control structure (see figure 22 - rx_sar control structure) to determine how to process the cell payload data.
mt90500 65 oam cell? oamsel vpi and vci timing vpi and vci match and mask lookup table t-bits uksel send timing pulse and aal1 byte to clock recovery module no yes 1 0 timing match no timing match no match vpi/vci match 32-cell internal utopia fifo oam cell? no yes 00(unde?ned) 01 (non-cbr data) oam data cell placed in rx data cell fifo 10 (cbr traf?c) use rx_sar control structure address in look-up table 1 0 cell discarded primary rx port phy (checks hec) utopia interface incoming cell figure 26 - receive cell selection process cell discarded cell discarded data cell placed in rx data cell fifo unknown data cell placed in rx data cell fifo
mt90500 66 rx structure address 0 31 t 2 rr r 18 16 15 vpi (m bits) vci (n bits) 00 (lutbase + 00000) + vpvcc rx structure address t r r r rx structure address t rr r vc lookup table rx_sar control structure bs 0 7 8 15 last entry first entry average lead payload size current entry aal1 byte reserved rx_sar write pointer minimum lead maximum lead rx circular buffer base address v v v v v +00 +02 +04 +06 +08 +0a +0c +0e +10 +fc +fe s as 0 rx circular buffer base address rx circular buffer base address rx circular buffer base address rx circular buffer base address reserved r 20 18 17 0 3 4 rx structure address rxbase (from 4000) 0 0 0 0 rx circular buffer 20 0 5 6 rx circular buffer base address 0 0 0 0 0 0 rx_sar write pointer 0 12 or 20 0 rx circular buffer write address 0 7 data byte data byte data byte data byte r = reserved (should be set to all zeroes) t = entry type (00 = inactive/undefined; 01 = non-cbr data; 10 = cbr; 11 = reserved) 0 0 lutbase + 00000 figure 27 - mt90500 cell receive process
mt90500 67 4.5.4 non-cbr data cell reception ability as mentioned above, the mt90500 is capable of receiving non-cbr data cells as well as cbr cells. non-cbr cells can be received on the utopia bus and written into the user-de?ned receive data cell fifo in external memory, where they wait for the cpu to read them. there are 3 ways for cells to be identi?ed as data cells. first of all, oam cells may be treated as non-cbr cells if the oam routing select bit in the utopia control register (address 4000h, bit<5>) is set to 1. secondly, unknown cells may be considered as non-cbr cells if the unknown routing select bit (bit<6> of the utopia control register) is set to 1. finally, normal cells whose vpi and vci values correspond to those in the vpi and vci match registers located at 4012h and 4016h respectively, can be tagged as data if their entry in the look- up table is associated with a non-cbr entry. to write into the receive data cell fifo, the chip will use the receive data cell fifo base address register (address 4020h) and will write into the next available entry as tagged by the receive data cell fifo write pointer register (address 4022h), regardless of the value in the rx structure address ?eld of the look-up table entry. once this is done, the write pointer will be incremented. finally, the cpu should read the data contained in the fifo once the write pointer becomes greater than the read pointer. to do so, the cpu should access each of the 24 word entries corresponding to that cell (24 words * 2 bytes = 48 bytes, max. cell payload). once it has completed its task, the read pointer should be incremented to ensure the hardware knows the cell has been read. rx structure address (can be ignored) 0 31 01 2 rr r 18 16 15 (lutbase + 00000) + vpvcc t = 01 indicates a non-cbr data cell t = entry type (refer to figure 27, mt90500 cell receive process, on page 66 for details for non-data cells) r = reserved (should be set to all zeroes) figure 28 - look-up table non-cbr data entry
mt90500 68 should the cpu not read the appropriate data cells or should a huge concentration of non-cbr cells arrive consecutively on the primary utopia port, a receive data cell fifo overrun will occur. this error, indicated by bit<10> of the utopia status register (address 4002h), indicates that the oldest data cell in the fifo has been over-written due to lack of space for valid cells. should this occur, the cpu will have to read the non-cbr cells faster or, conversely, the receive data cell fifo size should be increased. vpi(7:0) gfc or vpi(11:8) 0 7 8 15 vci(11:0) +00 +02 +04 +06 data byte #3 data byte #2 data byte #45 data byte #44 data byte #47 data byte #46 pti, etc. vci(15:12) data byte #1 data byte #0 +30 +32 reserved reserved reserved reserved reserved reserved reserved reserved +34 +36 +38 +3a reserved reserved reserved reserved +3c +3e figure 29 - received non-cbr data cell internal format
mt90500 69 tdm bus interface logic tdm bus 16 lines 1024 x 64kbps (max.) main utopia interface from external phy tdm clock logic clock signals mt90500 external synchronous sram tdm module internal tdm frame buffer utopia module local tdm bus 32 x 64 kbps in / 32 x 64 kbps out rx circular buffers - one for each tdm channel being received rx_sar control structures - one for each vc vc look-up table ? ? ? ? ? ? external memory to internal memory control structure directs data from circular buffers to tdm channels dictate received data to be sent to specific rx circular buffers determines which vcs are controlled by which rx_sar control structures 32-cell primary receive queue rx utopia block, including oam and vpi/vci filtering clock recovery receive cell selection process (see figure 26 on page 65) figure 30 - overview of cbr data reception process
mt90500 70 4.6 clock recovery from atm link 4.6.1 adaptive clock recovery sub-module adaptive clock recovery is a ?exible method for tdm clock recovery from an atm link. there are several approaches to adaptive clock recovery, and the standards do not require a speci?c one, so adaptive clock recovery is termed non-standardized. the implementation given here is similar to the general outline in itu-t i.363.1. in the mt90500, adaptive clock recovery uses a reference 8 khz clock to generate the tdm clock signals. the tdm clocks are controlled by adjusting the reference 8 khz clock frequency according to the arrival rate of atm cells on a designated vc. as seen in figure 31, the reception rate of timing reference cells or 8 khz markers (ex_8ka) is used as the basis for the adaptive clock recovery scheme implemented by this sub-module. this block is responsible for generating (under software control) a reference clock signal (rxvclk) based on the rate of reception of the timing reference cells or markers. the sub-module additionally implements a state machine (seen in figure 32) which tracks the cell arrival rate, checks the cell sequence numbers for lost or misinserted cells or cells with bad snp ?elds (to a maximum of one), and adjusts for discrepancies. the adaptive clock recovery block consists of: ? a timing reference cell processing unit which generates an event (new_cell) every time a timing reference cell is received. a timing reference cell is de?ned as an aal1 cell whose vpi/vci matches that speci?ed in the vpi timing register (401ah) and the vci timing register (401ch). oam cells on the speci?ed vpi/vci are ignored, as they do not carry cbr data. the unit can compensate for a single lost or misinserted cell or bad sequence number protection (snp). it will also ?ag an out-of-sync error when more than one cell is lost, misinserted, or received with corrupted sequence number protection. snp-checking is enabled by setting the seq_crc_ena bit in the timing reference processing control register at 60a0h. if no timing reference cell is received within a certain period (user-de?nable by setting bits<9:0> in the same register), it will generate a loss of timing reference cell error. the state machine for this unit is shown in figure 32: div 8 counter new_cell ex_8ka clkx1 ex_8ka 0 1 divx register (60a8h) divx ratio register (60aah) rxvclk cell / 8 khz mclk timing reference cell processing event counter temp register clkx1 count registers (60a4h and 60a6h) event count register (60a2h) external pll cntupdate refsel<1:0> = 01 ref8kclk clkx1 clkx2 8 khz designated timing vc figure 31 - adaptive clock recovery sub-module (simpli?ed functional block diagram) mt90500
mt90500 71 ? the event counter, which keeps a running count of the timing reference cells or 8 khz markers received. the cell/8 khz bit in the timing reference processing control register (address 60a0h) is used to select whether clock recovery is based on timing reference cell arrival events, or 8 khz marker events. the event count register (60a2h) is updated every time the cntupdate bit is set high in the clock module general control register at 6080h. ? a counter which is incremented every eight cycles of clkx1. the output of this counter is sent to the temp register, which is updated every time the event counter is incremented. finally, the clkx1 count registers (60a4h and 60a6h) are updated every time the cntupdate bit is set high in the clock module general control register at 6080h. the rxvclk clock generation block is composed of: ? a programmable divider (divx register at address 60a8h) which divides the master ic clock (mclk) in order to obtain rxvclk. ? a division factor register (divx ratio register at address 60aah) which controls the ratio of divide-by-x to divide-by-(x+1). together, the adaptive clock recovery block and the rxvclk clock generation block allow the cpu to implement an adaptive algorithm which permits the locally generated tdm clock to track the remotely generated tdm clock. out of sequence (except 2nd next) 2nd next sequence next sequence previous sequence next sequence out_of_ sync in_sync lost_cell bad snp next sequence (good snp) bad_snp - when going to in_sync or bad snp state, generate one timing reference pulse for each timing cell received. (bad snp is bad sequence number protection, meaning a bad crc, or a bad par- ity bit.) - when going to lost cell state, generate two timing reference pulses. - when coming back to in_sync state from lost cell state, generate one pulse if next sequence received. do not generate pulse if previous sequence received, indicating an inverse-ordered cell condition. - when in out_of_sync state, do not generate timing pulses. if out_sync_ie bit is set at 6080h, and tim_inte is set at 0000h, an interrupt will be generated on entering out_of_sync. - if no timing reference cells or markers have been received within the time-out period set in the timing reference processing control register (60a0h), a loss of timing reference cells event will be indicated (loss_timrf in 6082h), and an interrupt will be generated if losscie is set at 6080h (and tim_inte is set at 0000h). next sequence figure 32 - timing reference cell processing state machine any consecutive error out of sync (any consecutive error)
mt90500 72 the adaptive clock recovery method operates on a single receive vc which is de?ned by the vci timing register and the vpi timing register. the clock recovery method is, brie?y, as follows: ? every (clkx1 * 8) clock period, counter 1 (clkx1 counter) is incremented. ? every time an 8 khz marker or a cell with the timing recovery id is received, counter 2 (event counter) is incremented. as well, the clkx1 counter value is latched to the temp register. ? periodically, the processor writes the cntupdate bit in clock module general control register (6080h) and reads both counters to determine if the local clock needs to be sped up or slowed down with respect to the remote clock. ? the local clock (rxvclk) frequency is then adjusted by controlling the contents of the divx (60a8h) and divx ratio (60aah) registers. please refer to the mt90500 programmers manual for an example of an adaptive clock recovery algorithm. 4.6.2 srts clock recovery description the synchronous residual time stamp (srts) method of clock recovery is standardized in itu-t i.363.1 and ansi t1.630. this section outlines the operation of the mt90500 during transmit srts generation and receive srts clock recovery. note that srts may be used in different applications than adaptive clock recovery because srts produces a clock which better meets public network speci?cations for jitter and wander, but requires a common (synchronous) atm physical layer reference clock at both ends. please refer to msan-171 - tdm clock recovery from cbr-over-atm links using the mt90500 for applications of synchronous residual time stamp clocking. please note that mitel has entered into an agreement with bellcore with respect to bellcores u.s. patent no. 5,260,978 and mitels manufacture and sale of products containing the srts function. however the purchase of this product does not grant the purchaser any rights under u.s. patent no. 5,260,978. use of this product or its re- sale as a component of another product may require a license under the patent which is available from bell communications research, inc., 445 south street, morristown, new jersey 07960. since all of the tdm data streams on the mt90500 serial bus are synchronized to a single clock and frame pulse, the srts clock recovery module generates a single clock, from a single source vc. although the mt90500 may receive several cbr vcs from various sources, the serial bus clocks can be locked only to one of the incoming vcs. similarly, only one speci?c vc is selected to transmit the srts information from the mt90500 device. the as (aal type) ?elds within the transmit control structure (see figure 16) and the rx_sar control structure (refer to figure 22) are used to designate the particular transmit and receive vcs that will carry the srts information. note that only aal1-type cells can be used to transmit srts data as the csi bit in the aal1 header byte is used to carry the information. 4.6.2.1 transmit srts operation in the transmit srts operation, the mt90500 compares the local service clock (derived from clkx1) to a divided-down version of the network clock (available at the fnxi input pin). the srts method uses a stream of residual time stamps (rts) to communicate the difference between a common reference clock (f nx , derived from the network) and a local service clock (f s , derived from the local tdm clock). if the same atm physical layer reference clock is available at both the origin and destination points (e.g. two different mt90500s), the service clock can be recovered at the destination using the common reference clock, the transmitted (remote) rts, and a locally-generated rts. within the mt90500 srts module, the rts service clock is derived from the tdm clock signals. the clkx1 main tdm bus clock is used to obtain a clock, f b , which represents the tdm byte frequency of the srts transmit vc. f b is equal to n * 8 khz, where n is the number of tdm input channels in the vc which is selected for srts transmission (f b is one-eighth of the service clock, f s ). to generate f b , n pulses are spaced more or less evenly within the 125 m s period de?ned by the input signal fsync. the number of pulses per period and their spacing are determined by the settings within the srts transmit gapping divider register at address 60b0h. for instance, if there are 64 channels in the srts vc, n = 64, and the resulting byte rate, f b , is 512 khz (t b = 125 m s / 64). in order to implement this con?guration, the register at 60b0h should be set as follows: tx_ch_per_vc = 3fh while the tx_gapping ?eld is set to 3h. (please refer to srts transmit gapping divider register, on page 109 for con?guration details.)
mt90500 73 a 4-bit rts value is generated once every period of the rts (t n ). since one rts value is carried by the csi bits in each 8-cell sequence, the period of the rts is the assembly time of 8 cells on the designated srts vc. the srts transmit byte counter register at 60b2h contains the number of payload bytes within an 8-cell sequence of the srts vc. the value in this register is used to divide the byte frequency f b to obtain the period of the rts. for pointerless aal1 structured data transfer, the number of bytes necessary to ?ll 8 cells is 376 (8 cells @ 47 bytes per cell). in nx64 aal1 sdt, the number of bytes required to ?ll 8 cells varies depending on the number of p-bytes sent within an 8-cell sequence, but it is generally set to 375 bytes (1 cell of 46 tdm payload bytes plus 7 cells of 47 tdm payload bytes). the srts transmit divider register shown in figure 33 generates a latch pulse which captures the value of a free-running counter clocked by the external signal f nx (the network reference clock, input at the fnxi pin). the latched value is the four-bit residual time stamp. multiple latches (a 5-deep fifo) are used to synchronize this clocking block with cell transmission (controlled by the transmit event schedulers). in order for the srts clock recovery method to operate correctly, the divided-down network clock, fnxi, must be properly derived. as stated in i.363.1: for sdh and non-sdh physical layers, a clock at frequency f 8 = 8 khz, synchronized to a common network clock, is available from which clocks at frequencies f nx = f 8 x (19440 / 2 k ) khz, where k = 0,1,2,...,12 can be derived. this set of derived frequencies can accommodate all service rates from 64 kbps up to the full capacity of the stm-1 payload. the exact value of f nx to be used is uniquely speci?ed since the frequency ratio is constrained by 1 f nx /f s < 2. for example, to support n = 24 (f s = 1.536 mhz) or n = 32 (f s = 2.048 mhz), the derived network frequency will be 2.430 mhz (8000 * 19440 / 2 6 ). to support n = 1 (f s = 64 kbps), the derived network frequency will be 75.9375 khz (8000 * 19440 / 2 11 ). in compliance with i.363.1, the mt90500 transmits the 4-bit rts values in the serial bit stream provided by the csi bits of successive odd-sequence-numbered sar-pdu headers (the even-numbered csi bits are available for other uses such as sdt pointers). the modulo-8 sequence count provides a frame structure over 8 bits in this serial bit stream. the msb of the rts is placed in the csi bit of the sar-pdu header with a sequence count of 1. due to the internal hardware design of the mt90500, the frequency of fnxi must be < mclk / 3. this places no restrictions on the srts vc as long as mclk is greater than 30 mhz. since the maximum structure size is 122 channels, the maximum value of f s = 7.808 mhz, and the maximum value of f nx is 9.72 mhz. 4 atm physical layer divide by x 4-bit counter f nx rts multiple clk data_in tx_sar block fnxi enable byte counter clkx1 period of the rts f b gapping control f b generator srts transmit divider register latches (one 8-cell cycle) 4 f b = f s / 8 = service byte clock network clock internal to mt90500 transmit atm cells w/ csi b its figure 33 - transmit srts operation
mt90500 74 4.6.2.2 receive srts operation note: the following speci?cation assumes that the mt90500 will perform the srts function with the use of external logic as depicted in figure 35 and figure 36. on the receive side, the mt90500 will generate a local rts value (expected_srts) as depicted in figure 34 (and in a manner identical to that explained in detail in section 4.6.2.1 for the transmit direction), and will compare it with the received rts code (rx_srts) from the incoming atm stream. up to ?ve locally- generated rts values can be stored in a series of internal latches (a 5-deep fifo). the mt90500 internal comparator generates a 4-bit complement code that indicates the difference between the locally generated rts value and the incoming rts value (remote - local). the value of this code ranges from -8 (1000) to +7 (0111). the result of the comparison is then sent out via the srtsdata pin, with an associated strobe output transmitted on srtsena. external user logic is necessary to monitor these difference values, perform the clock adjustment and recover the original st-bus clock. if the difference values increase, it is due to the fact that the remote bus is running faster than the local bus and therefore the local bus frequency must be increased. likewise, if the difference values are decreasing, it is because the remote bus is running more slowly than the local bus, and thus the local bus must be slowed down. two 5-deep fifos are used to minimize the effect of cell delay variation in the transmission and reception process and to minimize slips. for both the receive srts and the transmit srts processes, the fifos are self-aligning: if an underrun or overrun is encountered, the fifos pointers are re-centered. these errors are reported in the clock module general status register at 6082h. 4 divide by x 4-bit counter f nx multiple clk data_in figure 34 - receive srts operation fnxi enable byte counter clkx1 period of the rts f b gapping control f b generator srts receive divider register latches (one 8-cell cycle) 4 f b = f s / 8 = service byte clock comparator srtsena enable 4 srtsdata rx_srts expected_ srts rx_sar block atm physical layer network clock internal to mt90500 receive atm cells w/ csi b its
mt90500 75 (mvip, st-bus, scsa) srtsena srtsdata clkx1 fsync pll external local reference timing generation circuit (small fpga) atm phy device network reference clock utopia interface ex_8ka . figure 35 - clock recovery using srts method (hardware) pllclk ref8kclk note 1: in atm receive applications, srtsdata corresponds to the 4-bit srts calculated as the difference between the locally-generated rts code and the remotely-generated rts code received from the incoming atm cell stream. note 2: the external timing generation logic generates an 8 khz output reference clock. this signal is fed from the fpga into the ex_8ka input of the mt90500 to be routed back to the external pll. note 3: the external reference timing generation logic can be implemented in a small fpga. fnxi tdm port corsigc corsigd corsigb divide by x e.g. mt9041 mt90500 device
mt90500 76 (mvip, st-bus, scsa) srtsena srtsdata clkx1 fsync pll external data latch/buffer (small fpga) atm phy device network reference clock utopia interface . figure 36 - clock recovery using srts method (cpu) pllclk ref8kclk note 1: in atm receive applications, srtsdata corresponds to the 4-bit difference calculated between the locally-generated rts code and the remotely-generated rts code received from the incoming atm cell stream. note 2: the external circuit within the fpga provides access to the srtsdata values in a parallel format (i.e. stored in a register). note 3: the cpu then accesses the srts values stored within the fpga. a software algorithm is used to determine if the local clock is too fast or too slow relative to the remote clock. based on this algorithm, the divx and divx ratio registers are modi?ed (as in adaptive clock recovery). using the new settings in these registers, the mt90500 generates an 8 khz output reference clock from ref8kclk. this signal is routed from the mt90500 to the external pll. fnxi tdm port corsigc corsigd corsigb divide by x e.g. mt9041 mt90500 device cpu running srts s/w algorithm modi?ed divx and divx ratio values
mt90500 77 4.7 microprocessor interface 4.7.1 general this interface allows an external control device (microprocessor) to con?gure and con?rm the status of the mt90500 via access to internal control and status registers and access to the external device memories. it supports a variety of software maskable interrupt services. the cpu interface allows external microprocessors to program the mt90500 and its external memory. the interface supports word (16-bit) data accesses only. the aem pin determines if the access is to internal registers (0), or to external memory (1). the cpu module features internal registers that are used to control and monitor the operation of the mt90500. see main control register (0000h) and main status register (0002h) in section 5.2. detailed timing diagrams for the microprocessor interface are shown in section 6.2.3, cpu interface - accessing registers and external memory. 4.7.2 a programming example - how to set up a vc the basic sequence for initializing a connection at the mt90500 can be summarized in 5 functional steps. in outlining the basic steps, we consider the need to allocate an atm virtual circuit to one or more 64 kbps channels present at the st-bus interface (st[15:0]). in this particular scenario, we focus on a channel to be received from the st-bus interface and sent out at the atm interface (i.e. the transmit process). a similar procedure (albeit in the reverse order) will have to be repeated for the case whereby an atm vc is received and transferred to the associated 64 kbps channel at the st-bus interface (i.e. the receive process). 1 - the cpu identi?es which 64 kbps time slot(s) or n x 64 kbps grouped channel(s) must be selected on the st-bus backplane. the identi?cation of the selected channels is done via a command from the driver managing the device. 2 - the cpu identi?es which of the transmit circular buffers are available to receive the 64 kbps time slots from the st-bus interface. the number of circular buffers available will depend on the number of time slots and the data rate selected at the st-bus backplane interface (256 time slots @ 2.048 mbps, 512 time slots @ 4.096 mbps or 1024 time slots @ 8.192 mbps). 3 - once the selection of the circular buffers is made, the cpu maps the time slots to be serviced and therefore to be transferred to the external circular buffers. this is performed via programmable pointers in the transmit circular buffer control structure, located in external memory. 4 - the cpu starts ?lling the transmit control structure(s). this information is programmed in external memory and identi?es (in summary) the atm cell header bytes, the circular buffer address(es) from which the device will take the time slots and assemble cells, and whether or not this is a partially-?lled cell. 5 - once the atm cell structure for a particular vc is complete, the cpu can program the scheduler, which basically tells the mt90500 how many and which tasks must be executed every 125 m s. if multiple atm virtual circuits have to be opened simultaneously, the cpu can execute items 1 to 4 taking into consideration all the tdm channels being treated. however, item 5 can be optimized to provide some fairness in the general tx_sar engine so that the device can perform up to 1024 speci?c atm vc cell assembly functions using minimal memory and processing time requirements. the details of that operation, as well as speci?c vc setup examples, are provided in the mt90500 programmers manual.
mt90500 78 4.7.3 microprocessor access and device reset upon hardware reset (using the reset pin) of the mt90500, the microprocessor registers go to their respective reset states, as indicated in the register descriptions. further, the sres bit in register 0000h is set low, latching the reset state. no registers other than the microprocessor interface registers can (nor should) be accessed until the sres bit is set high. steps to reset and restart the mt90500 are therefore: 1. assert hardware reset (and optionally trist a te), or write register 0000h to 0000h. 2. remove hardware reset. 3. allow at least 75 mclk clock cycles (about 2 m sec at 60 mhz). 4. write register 0000h to 4400h (enable normal internal clocks). 5. write register 0000h to c400h (de-assert sres). 6. write register 0000h to desired functional setting. 7. write other mt90500 registers. (note that con?guration bits must generally be programmed before setting process enable bits.) 4.8 test interface the mt90500 contains an ieee 1149 standard test access port (tap), which provides boundary-scan test access to aid board-level testing. (ieee 1149 is often referred to by its older designation: jtag - joint test action group.) 4.8.1 test access port the test port is a standard ieee 1149 interface, with the optional trst pin. the test access port consists of 5 pins: tclk : boundary-scan test clock. tdi : test data in; input pin clocked in on the rising edge of tck. tdi should be pulled high if bound- ary-scan is not in use. tdo : test data out; output pin updated on the falling edge of tck. the output is in high-impedance except when data is actually being shifted out. tms : test mode select; input control line clocked in on the rising edge of tck. tms should be pulled high if boundary-scan is not in use. trst : test reset; asynchronous, active-low, input which is used to reset the jtag interface, and the tap controller. the trst pin has an internal pull-down, and should also be pulled low externally whenever boundary-scan is not in use, to ensure normal operation of the mt90500. figure 37 below shows a typical board-level design, including how trst can be pulled high by the test connector in cases where the tester does not provide a trst pin.
mt90500 79 4.8.2 jtag id the jtag device id for the mt90500 is 0050014bh: version<31:28>: 0000 part number<27:12>: 0000 0101 0000 0000 = 0500h manufacturer id<11:1>: 0001 0100 101 lsb<0>: 1 4.8.3 boundary scan instructions the tap controller of the mt90500 supports the following instructions: idcode, sample, bypass, extest, highz, clamp, and intest. 4.8.4 bsdl a bsdl (boundary scan description language) ?le is available from mitel semiconductor to aid in the use of the ieee 1149 test interface. tclk tdi tdo tms jtag test connector figure 37 - a typical jtag test connection tclk tdi tdo tms gnd jtag tester signals board-under-test trst mt90500
mt90500 80 5. register map 5.1 register overview 5.1.1 general this section describes the registers contained within the mt90500. the mt90500 is mapped over 128 kbytes of address space, which is divided into two halves by the state of the aem input pin. the division of the addressing allows the user to access either the internal registers associated with the different internal blocks, or to access the external ssram containing the circular buffers and associated control structures. the ?rst 64 kbytes of address space are allocated for internal use, and are accessed by setting the aem input pin low. as shown in table 11 on page 82, the mt90500 does not implement all of the 64 kbytes available inside the chip. the unused address space is reserved for future functionality. the internal registers are used for control and status of: ? microprocessor interface ? tx_sar ? rx_sar ? utopia module and interface ? tdm interface and clock recovery ? tdm time slot control. the second 64 kbytes of address space are allocated as a window to external memory, accessed by setting the aem input pin high. this window is used by the cpu to access up to 2048 kbytes of external sram. the ?ve latched address bits (extmadd[20:16] located at 0030h), provide access to 32 pages (each 64 kbytes long) of external memory. all microprocessor accesses are 16-bit (word) accesses; byte access is not supported. note that addresses are however expressed as byte addresses. the least-signi?cant-bit of the address bus is the a1 pin, suf?cient to distinguish between 16-bit words. all register addresses and reset values are listed in hexadecimal (hex) format. the register types are: ? read / write (r/w) - can be read or written via the microprocessor interface. ? read only latched (r/o/l) - these bits are set by an activated status point within the chip; once set, they remain set even if the status point is deactivated. the microprocessor can read this point and clear it by writing a logic 1 into it. the register is cleared if the status point is not active. writ- ing logic 0 has no effect on this register. ? read only (r/o) - can be read via the microprocessor interface. a write to this register is ignored by the chip. ? write only (w/o) - certain bits associated with aal5 operation which must be written high, but which read back low.
mt90500 81 5.1.2 interrupt structure the mt90500 uses a two-level interrupt structure, as shown in figure 38. for each of ?ve major modules (tx_sar, rx_sar, utopia, tdm interface and tdm clock) there is a status register containing one or more status bits, and a control register containing corresponding mask bits (interrupt enable bits). there is also a main status register, and a main control register. for an interrupt to be asserted at the int pin, the following three conditions must be met: a status bit in one of the ?ve module status registers must be asserted by an alarm event; the mask bit for that alarm event must be set in that modules control register; and the mask bit for that module must be set in the main control register. similarly, an interrupt event at the int pin can be traced back to its source by reading the main status register to identify the module which is the source of the alarm, and then reading that modules status register to identify the particular alarm source. the interrupt can then be cleared by writing a 1 over the status bit. status register control register main status main control one for each major module figure 38. mt90500 interrupt structure status bits status mask . . . . . . . . . bits . . . . . . . . . register register . . . int
mt90500 82 5.1.3 register summary table 11 - register summary address hex label reset value description microprocessor interface registers 0000 mcr 0000 main control register 0002 msr 00x0 main status register 0010 reserved 0000 reserved - do not write 0012 reserved 0001 reserved - do not write 0030 wtemc 0000 window to external memory register - cpu 0032 reserved 0000 reserved - do not write 0034 reserved 0000 reserved - do not write 0036 rdpar 0000 read parity register 0040 memcnf 0008 memory configuration register tx_sar registers 2000 txsc 0000 tx_sar control register 2002 txss 0000 tx_sar status register 2010 tesbaa 0000 tx_sar scheduler base register - scheduler a 2012 tesfea 0000 tx_sar frame end register - scheduler a 2014 tesera 0000 tx_sar end ratio register - scheduler a 2020 tesbab 0000 tx_sar scheduler base register - scheduler b 2022 tesfeb 0000 tx_sar frame end register - scheduler b 2024 teserb 0000 tx_sar end ratio register - scheduler b 2030 tesbac 0000 tx_sar scheduler base register - scheduler c 2032 tesfec 0000 tx_sar frame end register - scheduler c 2034 teserc 0000 tx_sar end ratio register - scheduler c 2040 txcsba 0000 tx_sar control structure base address register 2050 txdfba 0000 transmit data cell fifo base address register 2052 txdfwp 0000 transmit data cell fifo write pointer register 2054 txdfrp 0000 transmit data cell fifo read pointer register rx_sar registers 3000 rxscr 0000 rx_sar control register 3002 rxssr 0000 rx_sar status register 3010 rxmeid 0000 rx_sar misc. event id register 3012 rxmect 0000 rx_sar misc. event counter register 3020 rxueid 0000 rx_sar underrun event id register 3022 rxuect 0000 rx_sar underrun event counter register 3030 rxoeid 0000 rx_sar overrun event id register 3032 rxoect 0000 rx_sar overrun event counter register utopia registers 4000 ucr 0000 utopia control register 4002 usr 0000 utopia status register 4010 vpvcc 0000 vpi / vci concatenation register 4012 vpmt 0000 vpi match register 4014 vpms 0000 vpi mask register 4016 vcmt 0000 vci match register 4018 vcms 0000 vci mask register 401a vpitim 0000 vpi timing register
mt90500 83 401c vcitim 0000 vci timing register 401e lutba 0000 look-up table base address register 4020 rxdfba 0000 receive data cell fifo base address register 4022 rxdfwp 0000 receive data cell fifo write pointer register 4024 rxdfrp 0000 receive data cell fifo read pointer register tdm interface and clock interface registers 6000 tdmcnt 0000 tdm interface control register 6002 tis xx00 tdm interface status register 6004 corsig 0000 tdm i/o register 6010 tdmtyp 0000 tdm bus type register 6020 lbtyp 0000 local bus type register 6022 tdmloc 0000 tdm bus to local bus transfer register 6024 loctdm 0000 local bus to tdm bus transfer register 6040 txcbcs 0000 tx circular buffer control structure base register 6042 emim 0000 external to internal memory control structure base register 6044 txcbba 0000 tx circular buffer base address register 6046 rxunda 0000 tdm read underrun address register 6048 rxundc 0000 tdm read underrun count register 6080 cmgcr 0000 clock module general control register 6082 cmgsr 0000 clock module general status register 6090 mcgcr 00c0 master clock generation control register 6092 mcdf 2000 master clock / clkx2 division factor 60a0 trpcr 0001 timing reference processing control register 60a2 evcr 0000 event count register 60a4 c1crl 0000 clkx1 count - low register 60a6 c1crh 0000 clkx1 count - high register 60a8 divx 2000 divx register 60aa divxr 0fff divx ratio register 60b0 srtgd 0000 srts transmit gapping divider register 60b2 srtbc 0177 srts transmit byte counter register 60b4 srrgd 0000 srts receive gapping divider register 60b6 srrbc 0177 srts receive byte counter register tdm time slot control 7000 + 2n oem xxxx output enable registers (n=0,1,2,....,127) table 11 - register summary address hex label reset value description
mt90500 84 5.2 register description 5.2.1 microprocessor interface registers table 12 - main control register address: 0000 (hex) label: mcr reset value: 0000 (hex) label bit position type description tdm_inte 0 r/w tdm module interrupt enable. enables interrupts from the tdm module when 1. see tdm_serv in register 0002h. tx_sar_inte 1 r/w tx_sar module interrupt enable. enables interrupts from the tx_sar module when 1. see tx_sar_serv in register 0002h. rx_sar_inte 2 r/w rx_sar module interrupt enable. enables interrupts from the rx_sar module when 1. see rx_sar_serv in register 0002h. mux_inte 3 r/w utopia mux sub-module interrupt enable. enables interrupts from the utopia module when 1. see mux_serv in register 0002h. tim_inte 4 r/w timing recovery module interrupt enable. enables interrupts from the timing recovery module when 1. see tim_serv in register 0002h. reserved 10:5 r/w reserved. must be set to 100_000. page_mode 11 r/w for normal operation, set this bit to 1. ptxclk_sel 13:12 r/w ptxclk select. choose how ptxclk is generated. 00= ptxclk pin is tristated (external oscillator drives the pin); 01= mclk/2; 10= mclk/4; 11=stxclk. clockmod 14 r/w clock mode. when 0, all external clocks (except mclk) are replaced by mclk/4. when 1, all clocks operate normally. this feature ensures that all internal blocks in the mt90500 are reset even if some secondary clocks are absent. to prevent internal clock glitches, this bit should be set before sres is de-asserted. sres 15 r/w software reset. when 0, all modules except the cpu module are maintained in a reset state. note that the mt90500 is synchronously reset, and that mclk should be applied during reset. reset should last at least 2 m sec when mclk is 60 mhz (>75 clock cycles). note: sres should be written to 1 before any other register is accessed. table 13 - main status register address: 0002 (hex) label: msr reset value: 00x0 (hex) label bit position type description tdm_serv 0 r/o tdm module service request. when 1, indicates the tdm module requires service (i.e. at least one tdm interface event bit (in register 6002h) and matching enable bit (in register 6000h) are set). when this bit is 1 and the tdm_inte interrupt enable bit is 1 in the mcr (register 0000h), an external hardware interrupt is generated. tx_sar_serv 1 r/o tx_sar module service request. when 1, indicates the tx_sar module requires service (i.e. at least one tx_sar event bit (in register 2002h) and matching enable bit (in register 2000h) are set). when this bit is 1 and the tx_sar_inte interrupt enable bit is 1 in the mcr (register 0000h), an external hardware interrupt is generated. rx_sar_serv 2 r/o rx_sar module service request. when 1, indicates the rx_sar module requires service (i.e. at least one rx_sar event bit (in register 3002h) and matching enable bit (in register 3000h) are set). when this bit is 1 and the rx_sar_inte interrupt enable bit is 1 in the mcr (register 0000h), an external hardware interrupt is generated. mux_serv 3 r/o utopia mux sub-module service request. when 1, indicates the utopia mux sub- module requires service (i.e. at least one utopia event bit (in register 4002h) and matching enable bit (in register 4000h) are set). when this bit is 1 and the mux_inte interrupt enable bit is 1 in the mcr (register 0000h), an external hardware interrupt is generated.
mt90500 85 tim_serv 4 r/o timing module service request. when 1, indicates the timing recovery module requires service (i.e. at least one clock recovery event bit (in register 6082h) and matching enable bit (in register 6080h) are set. when this bit is 1 and the tim_inte interrupt enable bit is 1 in the mcr (register 0000h), an external hardware interrupt is generated. reserved 6:5 r/0 reserved. undefined at reset. service 7 r/o 1 when any of bits<4:0> is set. undefined at reset. reserved 15:8 r/o always read 0000_0000 table 14 - window to external memory register - cpu address: 0030 (hex) label: wtemc reset value: 0000 (hex) label bit position type description extmadd16 0 r/w this bit represents address line a[16] for external memory access (cpu byte address). this bit maps to mem_add[14] (double-word address). extmadd17 1 r/w this bit represents address line a[17] for external memory access. this bit maps to mem_add[15] or bank_selection (32k addressing mode). extmadd18 2 r/w this bit represents address line a[18] for external memory access. this bit maps to mem_add[16] or bank_selection (64k addressing mode). extmadd19 3 r/w this bit represents address line a[19] for external memory access. this bit maps to mem_add[17] or bank_selection (128k addressing mode). extmadd20 4 r/w this bit represents address line a[20] for external memory access. this bit maps to bank_selection (256k addressing mode). reserved 15:5 r/w reserved, must always be 0000_0000_000. this register is automatically used while a cpu access is performed. table 15 - read parity register address: 0036 (hex) label: rdpar reset value: 0000 (hex) label bit position type description cpupar32 0 r/o bit 32 corresponds to the parity bit of the ms byte of the last odd word read from the external memory by the cpu. cpupar33 1 r/o bit 33 corresponds to the parity bit of the ls byte of the last odd word read from the external memory by the cpu. cpupar34 2 r/o bit 34 corresponds to the parity bit of the ms byte of the last even word read from the external memory by the cpu. cpupar35 3 r/o bit 35 corresponds to the parity bit of the ls byte of the last even word read from the external memory by the cpu. reserved 7:4 r/o reserved. reserved 15:6 r/o reserved. always read 0000_0000. table 13 - main status register address: 0002 (hex) label: msr reset value: 00x0 (hex) label bit position type description
mt90500 86 table 16 - memory con?guration register address: 0040 (hex) label: memcnf reset value: 0008 (hex) label bit position type description addmode 1:0 r/w addressing mode. indicates the number of address lines connected to the external memory and therefore the size of the memory chip(s). 00=32k (mem_add[14:0]); 01=64k (mem_add[15:0]); 10=128k (mem_add[16:0]); 11=256k (mem_add[17:0]). cpbank 2 r/w external memory chips per bank. indicates the number of external memory devices used in one memory bank. 0=1 x 32 (36)-bit chip; 1=2 x 16 (18)-bit chips. readlen 5:3 r/w read length. indicates the number of clock cycles between an address and its read data. 001=1 clock cycle (used with synchronous burst rams); 010=2 clock cycles (used with pipeline synchronous burst rams); 100=3 clock cycles; all other values are reserved. writing a reserved value in this register may have adverse effects on the mt90500 and the external memories. rwta 6 r/w read/write turn around cycles. 0=disabled; 1=enabled. rrta 7 r/w read bank1 / read bank2 turn around cycles. 0=disabled; 1=enabled. 8 r/w 9 r/w 10 r/w reserved 15:8 r/w reserved. these bits must always be 0000_0000 during operation. for further details on memory configuration, see section 4.2, external memory controller, on page 38.
mt90500 87 5.2.2 tx_sar registers table 17 - tx_sar control register address: 2000 (hex) label: txsc reset value: 0000 (hex) label bit position type description saena 0 r/w scheduler a enable. 0 = disabled; 1 = enabled. before enabling this scheduler, all its configuration registers must be written and valid. these registers must not be changed while saena is high. if an event scheduler is re-configured (i.e. changes made to 2010h, 2012h, or 2014h), all of its events and dependent structures should be re-initialized before starting the scheduler again. sbena 1 r/w scheduler b enable. 0 = disabled; 1 = enabled. before enabling this scheduler, all its configuration registers must be written and valid. these registers must not be changed while sbena is high. if an event scheduler is re-configured (i.e. changes made to 2020h, 2022h, or 2024h), all of its events and dependent structures should be re-initialized before starting the scheduler again. scena 2 r/w scheduler c enable. 0 = disabled; 1 = enabled. before enabling this scheduler, all its configuration registers must be written and valid. these registers must not be changed while scena is high. if an event scheduler is re-configured (i.e. changes made to 2030h, 2032h, or 2034h), all of its events and dependent structures should be re-initialized before starting the scheduler again. txffena 3 r/w transmit fifo enable. when this bit is low, the transmit data cell fifo read pointer (txffrp in txdfrp at 2054h) is reset to 00h. when this bit is high, the fifo can operate normally. autodata 4 r/w when this bit is 1, non-cbr data cells (the next cells located in the transmit data cell fifo) will be transmitted while the tx_sar is idle. when this bit is 0, data cell transmission is controlled by the schedulers. txfforie 5 r/w transmit data cell fifo overrun error interrupt enable. 0 = disabled; 1 = enabled. when enabled, a 1 on txffor in register 2002h will force a 1 on tx_sar_serv in register 0002h. schedule_ie 6 r/w scheduler error interrupt enable. 0 = disabled; 1 = enabled. when enabled, a 1 on schedule in register 2002h will force a 1 on tx_sar_serv in register 0002h. txffrp+ 7 r/w increment transmit data cell fifo read pointer. when 1 is written to this bit, the transmit data cell fifo read pointer (txffrp) is incremented. used for test purposes only. tests 8 r/w test status. when high, this bit forces all the status events in tx_sar status register at 2002h to occur. used for test purposes only. reserved 15:9 r/o reserved. always read as 0000_000. table 18 - tx_sar status register address: 2002 (hex) label: txss reset value: 0000 (hex) label bit position type description reserved 4:0 r/o reserved. always read as 0_0000. txffor 5 r/o/l transmit data fifo overrun. when set, this bit indicates that the cpu changed the value of the transmit data cell fifo write pointer (2052h) to the value of the transmit data cell fifo read pointer (2054h). when this event occurs, the mt90500 assumes that the cpu is trying to write one more non-cbr cell than the fifo can contain. writing a 1 over this bit clears it.
mt90500 88 schedule 6 r/o/l scheduler error. the tx_sar has too heavy a work load (e.g. too many events per scheduler frame; uneven distribution of events throughout the scheduler). to recover, the schedulers must be stopped and re-balanced. the tx control structures must also be re- initialized. writing a 1 over this bit clears it. fatal error. reserved 14:7 r/o reserved. always read as 000_0000_0. txserv 15 r/w tx service. this bit is set if bit<5> or bit<6> is set. table 19 - tx_sar scheduler base register address: scheduler a: 2010 (hex); scheduler b: 2020 (hex); scheduler c: 2030 (hex) label: tesbaa; tesbab; tesbac reset value: 0000 (hex) label bit position type description sbase 11:0 r/w scheduler base address. this register contains bits<20:9> of the base address of an event scheduler. bits<8:0> are always 000h. this register must not be changed when the scheduler is enabled. entry 15:12 r/w entries per frame. this register contains the number of entries in one frame on the scheduler. 0000 = 8 entries; 0001 = 16 entries; 0010 = 32 entries; all other values are reserved. this register must not be changed when the scheduler is enabled. note: all scheduler entries must be read from external ssram to check if they are active or inactive. better memory-bandwidth effici ency is achieved with fewer entries-per-frame and events distributed throughout the frames of the scheduler, as opposed to having burst s of events and many inactive entries. table 20 - tx_sar frame end register address: scheduler a: 2012 (hex); scheduler b: 2022 (hex); scheduler c: 2032 (hex) label: tesfea; tesfeb; tesfec reset value: 0000 (hex) label bit position type description shtend 7:0 r/w short end frame. this register indicates the number of the last frame when the scheduler is executing a short turn. this register must not be changed when the scheduler is enabled. lngend 15:8 r/w long end frame. this register indicates the number of the last frame when the scheduler is executing a long turn. this register must not be changed when the scheduler is enabled. table 21 - tx_sar end ratio register address: scheduler a: 2014 (hex); scheduler b: 2024 (hex); scheduler c: 2034 (hex) label: tesera; teserb; teserc reset value: 0000 (hex) label bit position type description ratio 2:0 r/w long/short ratio. this register indicates how many long turns a scheduler must execute for one short turn. in other words, the value in this register is the non-p: p-cell ratio. for pointerless cells, the value must be 000. for structured cells, the value can be 001 (1:1), 011 (3:1), or 111 (7:1). this register must not be changed when the scheduler is enabled. table 18 - tx_sar status register address: 2002 (hex) label: txss reset value: 0000 (hex) label bit position type description
mt90500 89 single 3 r/w single frame assembly. when 1, this bit indicates that cells must be assembled one frame at a time, which allows an even cell flow. when it is 0, it indicates that cells are formed 4 frames at a time, which allows better external memory efficiency. this register must not be changed when the scheduler is enabled. for full 1024 vc (or 1024 tdm time slot) operation, this bit must be 0. reserved 5:4 r/w reserved. these bits must always be written as 00. aal5_init 7:6 w/o initialization bits for aal5 operation. these two bits must be written, at initialization, in all three schedulers for aal5 operation in any scheduler, regardless of how many schedulers are active. the init pattern is different in each of the three schedulers: 2014h, scheduler a(7:6): 01 2024h, scheduler b(7:6): 10 2034h, scheduler c(7:6): 11 reserved 15:8 r/o reserved. these bits must always be 0000_0000. table 22 - tx_sar control structure base address register address: 2040 (hex) label: txcsba reset value: 0000 (hex) label bit position type description txbase 4:0 r/w tx control structure base address. when accessing a transmit control structure, txbase represents address bits<20:16>; the address in the scheduler, bits<15:4>. this register must not be changed when any scheduler is enabled. reserved 15:5 r/o reserved. always read as 0000_0000_000. table 23 - transmit data cell fifo base address register address: 2050 (hex) label: txdfba reset value: 0000 (hex) label bit position type description txffbase 11:0 r/w transmit data cell fifo base address. represents address bits<20:9> that point to the first structure in the transmit data cell fifo. the lower bits of this pointer are 0_0000_0000. each non-cbr cell occupies a 64-byte buffer. the transmit data cell fifo must not overlap an 8 kbyte boundary. when this register is changed, txffena (in the tx_sar control register at 2000h) must not be asserted. txffsiz 13:12 r/w transmit data cell fifo size. this field indicates the number of non-cbr data cells in the transmit data cell fifo. 00=16 cells; 01=32 cells; 10=64 cells; 11=128 cells. when this register is changed, txffena (in the tx_sar control register at 2000h) must not be asserted. reserved 15:14 r/w reserved. always read as 00. table 24 - transmit data cell fifo write pointer register address: 2052 (hex) label: txdfwp reset value: 0000 (hex) label bit position type description txffwp 7:0 r/w transmit data cell fifo write pointer. indicates cell structure number in which the cpu is currently writing (the cell is not yet valid) within the transmit data cell fifo. reserved 15:8 r/o reserved. always read as 00h. table 21 - tx_sar end ratio register address: scheduler a: 2014 (hex); scheduler b: 2024 (hex); scheduler c: 2034 (hex) label: tesera; teserb; teserc reset value: 0000 (hex) label bit position type description
mt90500 90 table 25 - transmit data cell fifo read pointer register address: 2054 (hex) label: txdfrp reset value: 0000 (hex) label bit position type description txffrp 6:0 r/o transmit data cell fifo read pointer. indicates the cell structure number in which the tx_sar is currently transmitting (the cell is still valid). reserved 15:7 r/o reserved. always read as 0000_0000_0.
mt90500 91 5.2.3 rx_sar registers table 26 - rx_sar control register address: 3000 (hex) label: rxscr reset value: 0000 (hex) label bit position type description apems 0 r/w aal1-byte parity error misc. select. when this bit is set, a parity error in the aal1-byte increments the rx_sar misc. event counter register (3012h) and affects the rx_sar misc. event id register (3010h). acems 1 r/w aal1-byte crc error misc. select. when this bit is set, a crc error in the aal1-byte increments the rx_sar misc. event counter register (3012h) and affects the rx_sar misc. event id register (3010h). snems 2 r/w aal1 sequence number error misc. select. when this bit is set, a sequence number error in the aal1-byte increments the rx_sar misc. event counter register (3012h) and affects the rx_sar misc. event id register (3010h). ppems 3 r/w pointer-byte parity error misc. select. when this bit is set, a parity error in the pointer-byte (for p-type cells only) increments the rx_sar misc. event counter register (3012h) and affects the rx_sar misc. event id register (3010h). porems 4 r/w pointer-byte out of range error misc. select. when this bit is set, an out of range pointer- byte (for p-type cells only) increments the rx_sar misc. event counter register (3012h) and affects the rx_sar misc. event id register (3010h). apeie 5 r/w aal1-byte parity error interrupt enable. 0 = disabled; 1 = enabled. when enabled, a 1 on ape in register 3002h will force a 1 on rx_sar_serv in register 0002h. aceie 6 r/w aal1-byte crc error interrupt enable. 0 = disabled; 1 = enabled. when enabled, a 1 on ace in register 3002h will force a 1 on rx_sar_serv in register 0002h sneie 7 r/w aal1-byte sequence number error interrupt enable. 0 = disabled; 1 = enabled. when enabled, a 1 on sne in register 3002h will force a 1 on rx_sar_serv in register 0002h ppeie 8 r/w pointer-byte parity error interrupt enable. 0 = disabled; 1 = enabled. when enabled, a 1 on ppe in register 3002h will force a 1 on rx_sar_serv in register 0002h poreie 9 r/w pointer-byte out of range error interrupt enable. 0 = disabled; 1 = enabled. when enabled, a 1 on pore in register 3002h will force a 1 on rx_sar_serv in register 0002h wureie 10 r/w write underrun error interrupt enable. 0 = disabled; 1 = enabled. when enabled, a 1 on wure in register 3002h will force a 1 on rx_sar_serv in register 0002h woreie 11 r/w write overrun error interrupt enable. 0 = disabled; 1 = enabled. when enabled, a 1 on wore in register 3002h will force a 1 on rx_sar_serv in register 0002h mcrie 12 r/w misc. counter rollover interrupt enable. 0 = disabled; 1 = enabled. when enabled, a 1 on mcr in register 3002h will force a 1 on rx_sar_serv in register 0002h wurcrie 13 r/w write underrun counter rollover interrupt enable. 0 = disabled; 1 = enabled. when enabled, a 1 on wurcr in register 3002h will force a 1 on rx_sar_serv in register 0002h worcrie 14 r/w write overrun counter rollover interrupt enable. 0 = disabled; 1 = enabled. when enabled, a 1 on worcr in register 3002h will force a 1 on rx_sar_serv in register 0002h tests 15 r/w test status. when high, this bit forces all the status events in the rx_sar status register at 3002h to occur. also increments the rx_sar misc. event counter register (3012h), the rx_sar underrun event counter (3022h), and the rx_sar overrun event counter (3032h) and affects the contents of the rx_sar misc. event id register (3010h), the rx_sar underrun event id register (3020h), and the rx_sar overrun event id register (3030h). used for test purposes only.
mt90500 92 table 27 - rx_sar status register address: 3002 (hex) label: rxssr reset value: 0000 (hex) label bit position type description reserved 4:0 r/o reserved. always read as 0_0000. ape 5 r/o/l aal1-byte parity error. 0 = event has not occurred. 1 = event has occurred. writing a 1 over this bit clears it. ace 6 r/o/l aal1-byte crc error. 0 = event has not occurred. 1 = event has occurred. writing a 1 over this bit clears it. sne 7 r/o/l aal1-byte sequence number error. 0 = event has not occurred. 1 = event has occurred. writing a 1 over this bit clears it. ppe 8 r/o/l pointer-byte parity error. 0 = event has not occurred. 1 = event has occurred. writing a 1 over this bit clears it. pore 9 r/o/l pointer-byte out of range error. 0 = event has not occurred. 1 = event has occurred. writing a 1 over this bit clears it. wure 10 r/o/l write underrun error. 0 = event has not occurred. 1 = event has occurred. writing a 1 over this bit clears it. wore 11 r/o/l write overrun error. 0 = event has not occurred. 1 = event has occurred. writing a 1 over this bit clears it. mcr 12 r/o/l misc. counter rollover. if set, the rx_sar misc. event counter register at 3012h has rolled over. writing a 1 over this bit clears it. wurcr 13 r/o/l write underrun counter rollover. if set, the rx_sar underrun event counter register at 3022h has rolled over. writing a 1 over this bit clears it. worcr 14 r/o/l write overrun counter rollover. if set, the rx_sar overrun event counter register at 3032h has rolled over. writing a 1 over this bit clears it. rxserv 15 r/o/l rx service. this bit is set if any of bits<14:5> in this register is set. writing a 1 over this bit clears it. table 28 - rx_sar misc. event id register address: 3010 (hex) label: rxmeid reset value: 0000 (hex) label bit position type description miscid 15:0 r/w misc. event id number. this 16-bit register holds bits<19:4> of the address of the rx control structure that caused the last miscellaneous error. this register is only affected by the miscellaneous errors that are selected via the 5 least significant bits of the rx_sar control register (3000h). this register will also be updated if the tests bit is set in the rx_sar control register. table 29 - rx_sar misc. event counter register address: 3012 (hex) label: rxmect reset value: 0000 (hex) label bit position type description miscc 15:0 r/w misc. event count. this 16-bit registers value is incremented each time a miscellaneous error occurs. a miscellaneous error is considered to have occurred if any of bits<9:5> in the rx_sar status register at 3002h is set and the corresponding miscellaneous select bit in bits<4:0> of the rx_sar control register (3000h) is also set. this register is also incremented if tests is set in the rx_sar control register.
mt90500 93 table 30 - rx_sar underrun event id register address: 3020 (hex) label: rxueid reset value: 0000 (hex) label bit position type description wurid 15:0 r/w rx_sar write underrun id number. this 16-bit register holds bits<19:4> of the address of the rx control structure that caused the last write underrun error. this register will also be updated if the tests bit is set in the rx_sar control register at 3000h. table 31 - rx_sar underrun event counter register address: 3022 (hex) label: rxuect reset value: 0000 (hex) label bit position type description wurc 15:0 r/w rx_sar write underrun count. this 16-bit registers value is incremented each time a write underrun occurs or if the tests bit is set in the rx_sar control register at 3000h. table 32 - rx_sar overrun event id register address: 3030 (hex) label: rxoeid reset value: 0000 (hex) label bit position type description worid 15:0 r/w rx_sar write overrun id number. this 16-bit register holds bits<19:4> of the address of the rx control structure that caused the last write overrun error. this register will also be updated if the tests bit is set in the rx_sar control register at 3000h. table 33 - rx_sar overrun event counter register address: 3032 (hex) label: rxoect reset value: 0000 (hex) label bit position type description worc 15:0 r/w rx_sar write overrun count. this 16-bit register is incremented each time a write overrun occurs or if the tests bit is set in the rx_sar control register at 3000h.
mt90500 94 5.2.4 utopia registers table 34 - utopia control register address: 4000 (hex) label: ucr reset value: 0000 (hex) label bit position type description rxena 0 r/w rx cell enable. when 0, all received cells are ignored. when 1, received cells are processed normally. stxena 1 r/w secondary tx cell enable. when this bit is 0, no cells may be received from the secondary tx interface. when 1, the utopia module receives cells from the secondary sar normally. rrp 2 r/w round-robin priority. when 0, cbr traffic from the mt90500 has priority over traffic from the secondary sar interface. when 1, both traffic types have the same priority. rxffena 3 r/w receive fifo enable. when this bit is low, the receive data cell fifo write pointer (rxffwp at 4022h) is reset to 00h. when this bit is high, the fifo can operate normally. rxffwp+ 4 r/w increment receive data cell fifo write pointer. when 1 is written on this bit, the receive data cell fifo write pointer (rxffwp at 4022h) is incremented. used for test purposes only. oamsel 5 r/w oam routing select. 0 = discard; 1= treat as non-cbr data cell. uksel 6 r/w unknown routing select. 0 = discard cells with undefined entry types (i.e. t bits = 00 in look-up table); 1= treat cells with undefined entry types (i.e. t bits = 00 in look-up table) as non-cbr data cells. rxbase 9:7 r/w rx control structure base address. these three bits represent the three most significant address bits<20:18> of the pointer to the receive control structures. rxfforie 10 r/w receive data cell fifo overrun error interrupt enable. 0 = disabled; 1 = enabled. when enabled, a 1 on rxffor in register 4002h will force a 1 on mux_serv in register 0002h. rxorie 11 r/w rx utopia module internal fifo overrun interrupt enable. 0 = disabled; 1 = enabled. when enabled, a 1 on rxor in register 4002h will force a 1 on mux_serv in register 0002h. rxffrcie 12 r/w receive data fifo receive cell interrupt enable. 0 = disabled; 1 = enabled. when enabled, a 1 on rxffrc in register 4002h will force a 1 on mux_serv in register 0002h. reserved 14:13 r/w reserved. should be written as 00. tests 15 r/w test status. when high, this bit forces the three status events (bits<12:10>) in the utopia status register at 4002h to occur. used for test purposes only. table 35 - utopia status register address: 4002 (hex) label: usr reset value: 0000 (hex) label bit position type description reserved 9:0 r/o reserved. always read as 00_0000_0000. rxffor 10 r/o/l receive data cell fifo overrun error. when this bit is 1, the rxffwp (register 4022h) = rxffrp (register 4024h) and one or more non-cbr data cells were discarded because the receive data cell fifo was full. writing a 1 over this bit clears it. rxor 11 r/o/l receive utopia module internal fifo overrun. at least one cbr cell was lost because the rx_sar did not process the cells fast enough. writing a 1 over this bit clears it. rxffrc 12 r/o/l data fifo receive cell. each time a non-cbr data cell is received, this bit is set. writing a 1 over this bit clears it. reserved 14:13 r/o reserved. always read as 00. utoserv 15 r/o utopia service. when any of the status bits in this register are high, this bit is high.
mt90500 95 table 36 - vpi / vci concatenation register address: 4010 (hex) label: vpvcc reset value: 0000 (hex) label bit position type description n 4:0 r/w the n least significant bits of the vci to be used as an address in the vc look-up table. m 7:5 r/w the m least significant bits of the vpi to be used as an address in the vc look-up table. reserved 8 r/w reserved. must be written as 0. reserved 15:9 r/o reserved. always read as 0000_000. the vc search mechanism uses a table that can have up to 32k double-word (32-bit) entries. the table can therefore be 128 kbyte s long. this requires a 17-bit offset pointer formed by adding two least significant zeroes to a base 15-bit pointer. the base 15-bit p ointer is formed by concatenation of the n least significant bits of the vci with the m least significant bits of the vpi. the sum of m+n must b e at least 8 and a maximum of 15 . if m+n < 15, the most significant bits are zeroed. example: assume n=8, indicating that the 8 lsbs of the vci will be used to form the least significant part of the pointer. assu me m=4, indicating that the 4 lsbs of the vpi will be used to form the most significant portion of the pointer. since m+n = 12 < 15, bi ts<14:12> of the base pointer will be zeroed. assume the receive vpi value is 23h and the receive vci value is 5678h. the resulting base 15-bit pointer will be 0378. when two least significant 0 bits are added to form a 17-bit pointer, the result is 00de0h. this value is added to the look-up table base address register (401eh) contents to form a 21-bit address than can be located anywhere in memory. table 37 - vpi match register address: 4012 (hex) label: vpmt reset value: 0000 (hex) label bit position type description vpimatch 7:0 r/w vpi match value. vpi of received cells are compared to the value in this register to see if the cells should be passed to the internal fifo, or discarded. reserved 15:8 r/o reserved. always read as 00h. note: set the vpi match and mask filter as narrowly as practical for the application. see receive cell selection process on page 63. table 38 - vpi mask register address: 4014 (hex) label: vpms reset value: 0000 (hex) label bit position type description vpimask 7:0 r/w vpi mask value. each bit, when set, enables the comparison of the cell vpi and the vpimatch field. if a bit in this register is not set, the corresponding bit in the received cell vpi is considered valid, regardless of the setting in the vpimatch field. reserved 15:8 r/o reserved. always read as 00h. table 39 - vci match register address: 4016 (hex) label: vcmt reset value: 0000 (hex) label bit position type description vcimatch 15:0 r/w vci match value. vci of received cells are compared to the value in this register to see if the cells are valid. note: set the vci match and mask filter as narrowly as practical for the application. see receive cell selection process on page 63.
mt90500 96 table 40 - vci mask register address: 4018 (hex) label: vcms reset value: 0000 (hex) label bit position type description vcimask 15:0 r/w vci mask value. each bit, when set, enables the comparison of the cell vci and the vcimatch field. if a bit in this register is not set, the corresponding bit in the received cell vci is considered valid, regardless of the setting in the vcimatch field. table 41 - vpi timing register address: 401a (hex) label: vpitim reset value: 0000 (hex) label bit position type description timing vpi 7:0 r/w vpi of the timing reference vc. if the vpi_vci of the incoming cell matches that contained within this register and the vci timing register at 401ch, a clock pulse will be sent to the clock recovery module. reserved 15:8 r/o reserved. always read as 00h. table 42 - vci timing register address: 401c (hex) label: vcitim reset value: 0000 (hex) label bit position type description timing vci 15:0 r/w vci of the timing reference vc. if the vpi_vci of the incoming cell matches that contained within this register and the vpi timing register at 401ah, a clock pulse will be sent to the clock recovery module. table 43 - lookup table base address register address: 401e (hex) label: lutba reset value: 0000 (hex) label bit position type description lutbase 15:0 r/w look-up table base address. represents bits<20:5> of the pointer to the look-up table (bits<4:0> are 0_0000). it must point to a boundary larger than or equal to k * {2^(m+n+2)} bytes, where k = 0,1,2,... and m and n are those values obtained from vpi/ vci concatenation register at address 4010h. in addition, the look-up table requires an external memory allocation of 2^(m+n+2) bytes to accommodate the entire look-up table.
mt90500 97 table 44 - receive data cell fifo base address register address: 4020 (hex) label: rxdfba reset value: 0000 (hex) label bit position type description rxffbase 11:0 r/w receive data cell fifo base address. represents address bits <20:9> that point to the first structure in the receive data cell fifo. the lower address bits <8:0> of the pointer are 0_0000_0000. each cell occupies a 64-byte buffer. bit<0> of this field must always be 0. the receive data cell fifo must not overlap an 8 kbyte boundary. when this register is changed, ffena in the utopia control register at 4000h must not be asserted. rxffsiz 13:12 r/w receive data cell fifo size. this field contains the number of non-cbr data cells in the receive data cell fifo. 00=16 cells; 01=32 cells; 10=64 cells; 11=128 cells. when this register is changed, ffena in the utopia control register at 4000h must not be asserted. reserved 15:14 r/w reserved. always read as 00. table 45 - receive data cell fifo write pointer register address: 4022 (hex) label: rxdfwp reset value: 0000 (hex) label bit position type description rxffwp 7:0 r/o receive data cell fifo write pointer. indicates cell structure number in which the utopia module is currently writing (the cell is not valid yet) within the receive data cell fifo. reserved 15:8 r/o reserved. always read as 00h. table 46 - receive data cell fifo read pointer register address: 4024 (hex) label: rxdfrp reset value: 0000 (hex) label bit position type description rxffrp 7:0 r/w receive data cell fifo read pointer. indicates the cell structure number in which the cpu is currently reading (the cell is still valid). must be set by cpu as cells are read. reserved 15:8 r/o reserved. always read as 00h.
mt90500 98 5.2.5 tdm interface and clock interface registers table 47 - tdm interface control register address: 6000 (hex) label: tdmcnt reset value: 0000 (hex) label bit position type description tiena 0 r/w tdm to/from internal memory process enable. 0=disabled; 1=enabled. ieena 1 r/w internal to/from external memory process enable. 0=disabled; 1=enabled. genoe 2 r/w general output enable. enables tdm data outputs and inputs. 0 = tdm data output pins tristated and tdm output (i.e. receive) data is looped back as tdm input (i.e. transmit) data; 1 = normal tdm operation. in order to prevent collisions on the tdm bus, one should clear all of the output enable registers (addresses 7000 + 2n) prior to setting this bit. when low, disables cfail and cabs bits in the tdm interface status register (6002h). clk_loopback 3 r/w tdm clock loopback. 0 = normal operation; 1 = loopback. in loopback the clkx2, clkx1, and fsync input signals are replaced by the internally generated clocks, but the clock pins are not driven by the mt90500. cabsie 4 r/w clock absent interrupt enable. 0=disabled; 1=enabled. when enabled, a 1 on cabs in register 6002h will force a 1 on tdm_serv in register 0002h. cfailie 5 r/w clock fail interrupt enable. 0=disabled; 1=enabled. when enabled, a 1 on cfail in register 6002h will force a 1 on tdm_serv in register 0002h. tobie 6 r/w tdm out of bandwidth interrupt enable. 0=disabled; 1=enabled. when enabled, a 1 on tob in register 6002h will force a 1 on tdm_serv in register 0002h. trueie 7 r/w tdm read underrun error interrupt enable. 0=disabled; 1=enabled. when enabled, a 1 on true in register 6002h will force a 1 on tdm_serv in register 0002h. trucrie 8 r/w tdm read underrun counter rollover interrupt enable. 0=disabled; 1=enabled. when enabled, a 1 on trucr in register 6002h will force a 1 on tdm_serv in register 0002h. reserved 14:9 r/o reserved. always read as 000_000. tests 15 r/w test status. forces all status events in both the tdm interface status register (6002h) and the clock module general status register (6082h) to occur. also causes the tdm read underrun count register (6048h) to be incremented and the tdm read underrun address register (6046h) to be updated. used for test purposes only.
mt90500 99 table 48 - tdm interface status register address: 6002 (hex) label: tis reset value: xx00 label bit position type description reserved 3:0 r/o reserved. always read as 0000. cabs 4 r/o/l clock absent. this flag is raised when one or more of the three tdm clock pins (clkx2, clkx1, and fsync) has not changed state within a specified number of mclk cycles. the signals are monitored when the pins are inputs (tdm clock slave or clock master alternate modes), and also when the pins are outputs (tdm clock master mode). this flag is disabled when genoe is low. writing a 1 over this bit clears it. note when tclksyn in register 6010h is set to 1 in tdm slave mode, the clkx1 pin is not used as an output but remains high-impedance. the cabs bit will therefore report a loss of clocks unless an external signal is present at the clkx1 pin. cfail 5 r/o/l scsa clock fail. this flag is used only when the mt90500 is not the clock master (i.e. configured as slave or as clock master alternate in scsa mode). this flag is raised and latched when the clkfail pin is sampled high and the corsiga pin is configured as clkfail input (i.e. corsigacnf in 6004h must be 11). the corsiga bit in this register can be used to verify the current state of the clkfail signal. when this bit is high, and the clk_alt bit in 6010h is high, the mt90500 will drive the tdm clock lines (switch from master alternate to master) and if corsigacnf is 11, drive 0 out on corsiga/clkfail. this flag is disabled when genoe is low. writing a 1 over this bit clears it. tob 6 r/o/l tdm out of bandwidth. this flag is raised when the internal to/from external memory process is unable to transfer all the data in the specified time. this flag generally indicates that there is a bandwidth limitation in accesses to external memory. external memory access requirements must be reduced, or external memory speed must be increased. the ieena bit in the tdm interface control register at 6000h must be set for this error to be generated. writing a 1 over this bit clears it. true 7 r/o/l tdm read underrun error. 0 = error has not occurred. 1 = an underrun has occurred. indicates the occurrence of an underrun on a tdm read from one of the receive circular buffers. this error-indication is controlled by the tdm read underrun detection enable (u) bits in the external memory to internal tdm memory control structure (i.e. if the u bits are low, no underrun errors will be noted in this register). writing a 1 over this bit clears it. trucr 8 r/o/l tdm read underrun count rollover. this flag is raised when the underrun counter at register 6048h returns to 0000h. writing a 1 over this bit clears it. tdmserv 9 r/o tdm service bit. this bit is set if any of the above status bits<8:4> is set. reserved 10 r/o reserved. always read as 0. corsiga 11 r/o corsiga pins current logic level. undefined at reset. corsigb 12 r/o corsigb pins current logic level. undefined at reset. corsigc 13 r/o corsigc pins current logic level. undefined at reset. corsigd 14 r/o corsigd pins current logic level. undefined at reset. corsige 15 r/o corsige pins current logic level. undefined at reset.
mt90500 100 table 49 - tdm i/o register address: 6004 (hex) label: corsig reset value: 0000 (hex) label bit position type description corsigacnf 1:0 r/w corsiga configuration. selects operation of the corsiga pin. 00 general i/o pin configured as input (see corsiga bit in register 6002h) 01 general i/o pin configured as programmable output (see corsiga bit in this register) 10 reserved 11 clkfail i/o (see cfail at 6002h) - zero driven out when the mt90500 is clock master; clkfail input from scsa bus when in slave mode or inactive clock master alternate. corsigbcnf 3:2 r/w corsigb configuration. 00 general i/o pin configured as input 01 general i/o pin configured as programmable output (see corsigb bit in this register) 10 mc: i/o for scsa message channel (rxdata sent to corsigd; txdata read from corsigc 11 fnxi: srts fnx network clock input. corsigccnf 5:4 r/w corsigc configuration. 00 general i/o pin configured as input 01 general i/o pin configured as programmable output (see corsigc bit in this register) 10 hdlc mctx: data input for scsa message channel 11 srts ena output (there is a valid srts bit being transmitted on corsigd). corsigdcnf 7:6 r/w corsigd configuration. 00 general i/o pin configured as input 01 general i/o pin configured as programmable output (see corsigd bit in this register) 10 hdlc mcrx: data output for scsa message channel 11 srts data output from the clock recovery module. corsigecnf 9:8 r/w corsige configuration. 00 general i/o pin configured as input 01 general i/o pin configured as programmable output (see corsige bit in this register) 10 hdlc mcclk: clock output for scsa message channel 11 reserved. reserved 10 r/w reserved. should be set to 0. corsiga 11 r/w value that will be driven on corsiga output pin (only applicable if corsigacnf=01). corsigb 12 r/w value that will be driven on corsigb output pin (only applicable if corsigbcnf=01). corsigc 13 r/w value that will be driven on corsigc output pin (only applicable if corsigccnf=01). corsigd 14 r/w value that will be driven on corsigd output pin (only applicable if corsigdcnf=01). corsige 15 r/w value that will be driven on corsige output pin (only applicable if corsigecnf=01).
mt90500 101 table 50 - tdm bus type register address: 6010 (hex) label: tdmtyp reset value: 0000 (hex) label bit position type description tdmfs 1:0 r/w tdm fsync type. 00 = negative polarity for half-cycle of clkx1, straddling the frame boundary (scsa/ mvip/h-mvip/st-bus); 01 = reserved; 10 = reserved; 11 = positive polarity for full-cycle of clkx1, preceding the frame boundary (idl). when using the positive polarity frame sync, the mt90500 must be in master mode, or tclksyn (bit<6>) should be low, and the sc bus hdlc access will not function (pins mc, mcrx, mctx and mcclk). tdmsmpl 3:2 r/w tdm sampling. determines the sampling point of the serial input bit. 00 = 4/4; 01 = 3/4; 10 = 2/4; 11 = reserved. tdmclk 5:4 r/w tdm clock speed. determines the data rate of the tdm bus (and clkx1). 00 = 2 mhz, 32 time slots/frame; 01 = 4 mhz, 64 time slots/frame; 10 = 8 mhz, 128 time slots/frame; 11 = reserved. tclksyn 6 r/w selects source for internal clkx1. 0 = normal clkx1 output operation as tdm master, normal clkx1 input operation as tdm slave; 1 = derive clkx1 from clkx2 (slave mode where no clkx1 is provided by tdm bus) note that in tdm slave mode, with tclksyn = 1, the clkx1 pin is not used as an output but remains high-impedance. the cabs bit in register 6002h will therefore report a loss of clocks unless an external signal is present at the clkx1 pin. clktype 7 r/w clock type. selects operation of clkx2 input when tdm slave mode is selected (no effect when tdm master mode is selected). 0 = single-ended input (one input pin: clkx2); 1 = differential input (two input pins: clkx2pi and clkx2ni). clkmaster 8 r/w tdm clock master. 0 = mt90500 is tdm slave, and does not drive tdm clock pins (clkx2 is an input); 1 = mt90500 is tdm master, and drives the tdm clock pins (mt90500 drives clkx2, clkx1, and fsync). clkalt 9 r/w tdm clock alternate. 0 = disabled; 1 = mt90500 is designated as clock master alternate the clock master alternate will become the clock master and drive the clock lines only if the clock fail status bit (cfail in 6002h) is high. note : this bit is only used when corsigacnf in 6004h is 11, indicating that the corsiga pin is configured as clkfail input (scsa mode). reserved 10 r/w reserved. must always be set to 0. bushold 11 r/w bus hold time. 0 = fast bus (scsa 8 mbps); 1 = slow bus (mvip / scsa2 / idl / st-bus) reserved 15:12 r/o reserved. always read as 0000.
mt90500 102 table 51 - local bus type register address: 6020 (hex) label: lbtyp reset value: 0000 (hex) label bit position type description lbusfs 1:0 r/w local bus fsync type. 00 = negative polarity for half-cycle of locx1, straddling the frame boundary (scsa/ mvip/h-mvip/st-bus); 01 = reserved; 10 = reserved; 11 = positive polarity for full-cycle of locx1, preceding the frame boundary (idl). lbussmpl 3:2 r/w local bus sampling. 00 = 4/4; 01 = 3/4; 10 = 2/4; 11 = reserved. reserved 5:4 r/w reserved. should be written as 00. lclkdiv 7:6 r/w local bus clock division factor. amount that tdm backplane clock must be divided to generate 2.048 mbps local bus. 00 = direct; 01 = divided by 2; 10 = divided by 4; 11 = reserved. sti2locsto 11:8 r/w indicates which input tdm stream will be routed to locsto. locsti2sto 15:12 r/w indicates on which output tdm stream locsti will be routed. table 52 - tdm bus to local bus transfer register address: 6022 (hex) label: tdmloc reset value: 0000 (hex) label bit position type description tdm2locts 6:0 r/w locsto tdm time slot. input tdm time slot which will be transmitted out on locsto time slot 0. reserved 7 r/w reserved. should be written as 0. locstonum 14:8 r/w locsto number of time slots. number of time slots that are passed from the tdm bus to the local bus. 0000000 = 1 channel; 0011111 = 32 channels. tena 15 r/w transfer enable. when 0, the transfer process from the tdm bus to the local bus is disabled. when 1, the transfer is enabled. whenever the transfer of data from the tdm bus to the local bus is disabled (either because this bit is 0 or because the specified number of time slots has been transferred), locsti and locsto are internally connected and operate in loopback mode. note: the tiene bit at register 6000h must be set to 1 (tdm to/from internal memory transfer enabled) for the local bus to/from tdm bus transfer to operate.
mt90500 103 table 53 - local bus to tdm bus transfer register address: 6024 (hex) label: loctdm reset value: 0000 (hex) label bit position type description loc2tdmts 6:0 r/w locsti tdm time slot. output tdm time slot on which locsti time slot 0 will be transmitted. reserved 7 r/w reserved. should be written as 0. locstinum 14:8 r/w locsti number of time slots. number of time slots that are passed to the tdm bus from the local bus. 0000000 = 1 channel; 0011111 = 32 channels. rena 15 r/w receive enable. when '1', the transfer process is enabled and from 1 to 32 local bus time slots will replace the tdm data coming from the rx_sar. note: the tiene bit at register 6000h must be set to 1 (tdm to/from internal memory transfer enabled) for the local bus to/from tdm bus transfer to operate. note: the output enable registers must be enabled to permit these data bytes to be transferred out on the tdm bus. table 54 - tx circular buffer control structure base register address: 6040 (hex) label: txcbcs reset value: 0000 (hex) label bit position type description txcbcsl 3:0 r/w tx circular buffer control structure length. 0000 = 128 entries; 0001 = 256 entries; 0010 = 512 entries; 0011 = 1024 entries; 0100 = 2048 entries; other = reserved. txcbcsbase 15:4 r/w tx circular buffer control structure base address. this field represents bits<20:9> of the base address of the tx circular buffer control structure. the table that this structure points to must not cross an 8 kbyte boundary. refer to figure 5 on page 34 for implementation details. table 55 - external to internal memory control structure base register address: 6042 (hex) label: emim reset value: 0000 (hex) label bit position type description eimcsl 3:0 r/w external to internal memory control structure length. 0000 = 128 entries; 0001 = 256 entries; 0010 = 512 entries; 0011 = 1024 entries; 0100 = 2048 entries; other = reserved. eimcsbase 15:4 r/w external to internal memory control structure base address. this field represents bits<20:9> of the base address of the external to internal memory control structure. the table that this structure points to must not cross an 8 kbyte boundary. refer to figure 7 on page 37 for implementation details.
mt90500 104 table 56 - tx circular buffer base address register address: 6044(hex) label: txcbba reset value: 0000 (hex) label bit position type description reserved 3:0 r/w reserved. should be written as 0000. txcbbase 15:4 r/w tx circular buffer base address. this field represents bits<20:9> of the base address of the tx circular buffers base address. the pointer to the circular buffers must not overlap a 64 kbyte boundary. table 57 - tdm read underrun address register address: 6046 (hex) label: rxunda reset value: 0000 (hex) label bit position type description trurtsst 10:0 r/o tdm read underrun time slot stream. contains the time slot (bits<10:4>) and stream (bits<3:0>) on which the last underrun was detected. reserved 15:11 r/o reserved, always read as 0000_0. table 58 - tdm read underrun count register address: 6048 (hex) label: rxundc reset value: 0000 (hex) label bit position type description trurcount 15:0 r/o tdm read underrun counter. each time a tdm read underrun occurs, this registers value is incremented. table 59 - clock module general control register address: 6080 (hex) label: cmgcr reset value: 0000 (hex) label bit position type description reffailie 0 r/w reffail interrupt enable - clock generation sub-module. when enabled, a 1 on reffail in register 6082h will force a 1 on tim_serv in register 0002h. srtstsie 1 r/w srts transmit interrupt enable - srts sub-module. when enabled, a 1 on srtst_und or srtst_ovr in register 6082h will force a 1 on tim_serv in register 0002h. cntupdate 2 r/w counter update control - when a 1 is written to this bit, the counts in registers 0x60a2, 0x60a4, and 0x60a6 are updated. the values in those registers will remain the same until the next time a 1 is written to this bit. the static value of this bit is always ignored. srtsrsie 3 r/w srts receive interrupt enable - srts sub-module. when enabled, a 1 on srtsr_und or srtsr_ovr in register 6082h will force a 1 on tim_serv in register 0002h. reserved 4 r/w reserved. should be written as 0. losscie 5 r/w loss of timing reference cells interrupt enable - timing reference cell sub-module. when enabled, a 1 on loss_timf in register 6082h will force a 1 on tim_serv in register 0002h.
mt90500 105 out_sync_ie 6 r/w out-of-sync interrupt enable - timing reference cell sub-module. when enabled, a 1 on out_sync in register 6082h will force a 1 on tim_serv in register 0002h. tim_ena 7 r/w timing enable - when 1, enables the operation of the timing reference cell sub-module receive circuit for adaptive clock recovery. reserved 15:8 r/o will always read 00h. table 60 - clock module general status register address: 6082 (hex) label: cmgsr reset value: 0000 (hex) label bit position type description reffail 0 r/o/l reference clock failure - clock generation sub-module. when 1, indicates that the ref8kclk signal has failed. when this bit is 1 and the freerun bits in the master clock generation control register (mcgcr at 6090h) are 01, the external signal freerun will be activated. mclk should be at least 2048 times the ref8kclk frequency for proper operation. writing a 1 over this bit will clear it. srtst_und 1 r/o/l srts transmit underrun - srts sub-module. when 1, indicates a slip underrun error has occurred in the srts transmit circuit. this means that the tx_sar (scheduler) is sending rtss faster than the srts transmit divider register is generating them. check the scheduler vs. registers 60b0h, and 60b2h. can be ignored when srts transmission is not enabled. writing a 1 over this bit will clear it. srtst_ovr 2 r/o/l srts transmit overrun - srts sub-module. when 1, indicates a slip overrun error has occurred in the srts transmit circuit. this means that the srts transmit divider register is generating rtss faster than the tx_sar (scheduler) is sending them. check the scheduler vs. registers 60b0h, and 60b2h. can be ignored when srts transmission is not enabled. writing a 1 over this bit will clear it. srtsr_und 3 r/o/l srts receive underrun - srts sub-module. when 1, indicates a slip underrun error has occurred in the srts receive circuit. this means that the rx_sar is receiving rtss faster than the srts transmit divider register is generating rtss. check registers 60b4h, and 60b6h. can be ignored when srts reception is not enabled. writing a 1 over this bit will clear it. srtsr_ovr 4 r/o/l srts receive overrun - srts sub-module. when 1, indicates a slip overrun error has occurred in the srts receive circuit. this means that the srts transmit divider register is generating rtss faster than the rx_sar is receiving rtss. check registers 60b4h, and 60b6h. can be ignored when srts reception is not enabled. writing a 1 over this bit will clear it. loss_timrf 5 r/o/l loss of timing reference cell stream - timing reference cell sub-module. when 1, indicates a loss of timing reference cells (or marker) event has occurred (loss period determined by time-out field at 60a0h) while the adaptive clock recovery state machine was enabled (tim_ena bit set in clock module general control register at 6080h). writing a 1 over this bit will clear it. out_sync 6 r/o/l out-of-sync - timing reference cell sub-module. when 1, indicates the timing reference cell state machine went out of sync. this bit is set only when the state machine initially goes out of sync - if it stays out of sync., this bit will be cleared. writing a 1 over this bit will clear it. reserved 14:7 r/o will always read 000_0000_0. time_serv 15 r/o this bit is set if any of bits<6:0> are set. note: bits<6:0> will be set if the tests bit is set in the tdm interface control register at 6000h. table 59 - clock module general control register address: 6080 (hex) label: cmgcr reset value: 0000 (hex) label bit position type description
mt90500 106 table 61 - master clock generation control register address: 6090 (hex) label: mcgcr reset value: 00c0 (hex) label bit position type description refsel 1:0 r/w ref8kclk (8 khz reference clock) selection. see figure 3 on page 29. 00 -> mclk/(divclk + 2) or clkx2/(divclk + 2) (see register 6092h.) 01 -> rxvclk (recovered atm vc/sw clock. see register 60a8h.) 10 -> sec8k input pin 11 -> ex_8ka input pin. divclk_src 2 r/w selects input clock for programmable divider (see register 6092h.) 0 -> mclk 1 -> clkx2 ex_8ka_sq 3 r/w select squared version of ex_8ka for output. 0 -> pass ex_8ka signal without changes, 1 -> convert ex_8ka input to square wave. this bit, when high, selects the squared version of ex_8ka for routing to the ref8kclk, and the sek8k multiplexers. the squaring logic converts the ex_8ka input into a square wave (approximately 50% duty-cycle). this can convert a pulse 8 khz signal into an 8 khz square wave, for example. the rising edge of ex_8ka input is passed, without added jitter, to the ref8kclk or sec8k output as a falling edge (i.e. the signal is inverted); the rising edge at the ref8kclk output will be 50% duty cycle with jitter equal to a cycle of mclk. mclk must be at least 10 times faster, and at most 16000 times faster, than ex_8ka. see figure 3, tdm clock selection and generation logic, on page 29. sec8k_sq 4 r/w enable sec8k squaring logic. 0 -> pass sec8k signal without changes, 1 -> convert sec8k input to square wave. the squaring logic, when enabled, converts the sec8k input into a square wave (approximately 50% duty-cycle) before passing it to the ref8kclk multiplexer. this can convert a pulse 8 khz signal into an 8 khz square wave, for example. when refsel = 10 the rising edge of sec8k input is passed, without added jitter, to the ref8kclk output as a rising edge; the falling edge at the ref8kclk output will be 50% duty cycle with jitter equal to a cycle of mclk. mclk must be at least 10 times faster, and at most 16000 times faster, than sec8k. bepll 5 r/w clock generator multiplexer selection: selects clk16 input clock for the tdm clock generator. 0 -> mclk 1 -> pllclk input. div1...8 7:6 r/w clock generator division factor. (11 at reset) 00 -> 8 01 -> 1 10 -> 2 11 -> 4 note: these bits provide the factor by which either mclk or pllclk (as determined by bepll) is divided to provide a 16.384 mhz clock at the main tdm bus clock generation logic . phlen 8 r/w clock generator phase lock enable. when this bit is 1, and tdmfs (in the tdm bus type register at 6010h) is 00, the internal fsync signal generator will be slaved to the external fsync signal. this bit allows the mt90500 to be used as a clock master alternate in scsa mode (i.e. clkalt = 1 and clkmaster = 0 in tdm bus type register at 6010h). in this case, the stand-by clock master circuit (using clk16, the local 16.384 mhz clock derived from pllclk or mclk) tracks the external fsync signal so that when it is selected as a clock master after a clock failure, the new fsync will be almost in phase with the previous one. the phase-tracking is automatically disabled when the clkfail input pin is asserted. sec8ken 9 r/w when 1, the mt90500 drives the sec8k external signal. when 0, the sec8k pin is an input. sec8ksel 10 r/w sec8k clock source selection 0 -> ex_8ka 1 -> internally generated 8 khz reference ( fs_int )
mt90500 107 freerun 12:11 r/w clock failure detection - freerun signal control 00 -> freerun is always activated (freerun pin is high) 01 -> freerun is activated when status bit reffail (in the clock module general status register at 6082h) is 1. in the event of ref8kclk clock failure, it is the softwares responsibility to change the programming from 01 to 00 before clearing the reffail status bit. 1x -> freerun is always deactivated (freerun pin is low) reserved 15:13 r/w reserved. should be written as 000. refer to figure 3, tdm clock selection and generation logic, on page 29 for more detailed information regarding the implementat ion of the selection bits. table 62 - master clock / clkx2 division factor address: 6092 (hex) label: mcdf reset value: 2000 (hex) label bit position type description divclk 13:0 r/w this value plus two is used to divide mclk or clkx2 to get an 8 khz reference. value 0000h means divide-by-two, 0001h means divide-by-three, ..., 3ffeh means divide-by- 16,384. reserved 15:14 r/w reserved. should be written as 00. table 63 - timing reference processing control register address: 60a0 (hex) label: trpcr reset value: 0001 (hex) label bit position type description time-out 9:0 r/w this value is used to indicate a time-out period, after which if no timing reference cells or markers have been received, a loss of timing reference cells (loss_timrf in 6082h) event will be indicated. the time-out period is calculated in multiples of 65536 mclk periods. 00_0000_0000 is an illegal value (i.e. time-out is a minimum of 65536 cycles of mclk). cell / 8 khz 10 r/w when 0, indicates that clock recovery is based on timing reference cell arrival events. when 1, indicates that clock recovery is based on 8 khz marker arrival events. seq_crc_ena 11 r/w when 1, enable crc and parity checking on aal1 sequence number field in state machine. see figure 31 on page 70. reserved 15:12 r/w reserved. should be written as 0000. table 61 - master clock generation control register address: 6090 (hex) label: mcgcr reset value: 00c0 (hex) label bit position type description
mt90500 108 table 64 - event count register address: 60a2 (hex) label: evcr reset value: 0000 (hex) label bit position type description event_cnt 15:0 r/o this register keeps a running count of the reception of timing reference cells or 8 khz markers (as determined by setting of cell / 8 khz bit in register 60a0h). the contents of this register are locked when a 1 is written to the cntupdate bit in the clock module general control register (6080h). thus cntupdate should be set just prior to reading this register. see figure 31, adaptive clock recovery sub-module (simplified functional block diagram), on page 70 for more details. table 65 - clkx1 count - low register address: 60a4 (hex) label: c1crl reset value: 0000 (hex) label bit position type description clkx1_cnt_l 15:0 r/o this register represents the low portion of a 24-bit counter which keeps a running count of clkx1 * 8 periods (i.e. every 8 cycles of clkx1, a counter is incremented). the counter is updated at the same time the event count register (60a2h) is incremented. the contents of this register are locked when a 1 is written to the cntupdate bit in the clock module general control register (6080h). this should be done just prior to reading this register. see figure 31, adaptive clock recovery sub-module (simplified functional block diagram), on page 70 for more details. table 66 - clkx1 count - high register address: 60a6 (hex) label: c1crh reset value: 0000 (hex) label bit position type description clkx1_cnt_h 7:0 r/o this register represents the high portion of a 24-bit counter which keeps a running count of clkx1 * 8 periods (i.e. every 8 cycles of clkx1, a counter is incremented). the counter is updated at the same time the event count register (60a2h) is incremented. the contents of this register are locked when a 1 is written to the cntupdate bit in the clock module general control register (6080h). this should be done just prior to reading this register. see figure 31, adaptive clock recovery sub-module (simplified functional block diagram), on page 70 for more details. reserved 15:8 r/o unused. always read 00h.
mt90500 109 table 67 - divx register address: 60a8 (hex) label: divx reset value: 2000 (hex) label bit position type description divx 13:0 r/w this value is used (along with divxn, in the next register) to divide mclk to obtain an rxvclk reference. the average frequency of rxvclk is obtained as follows: note that when a new rxvclk setting requires a change to this register and to the divx ratio register, these two writes should be performed as closely together as possible. this is required to prevent drifting of the ref8kclk output frequency during the period that one register has been updated but the other hasnt. reserved 15:14 r/w reserved. should be written as 00. table 68 - divx ratio register address: 60aa (hex) label: divxr reset value: 0fff (hex) label bit position type description divxn 11:0 r/w this value defines how many times mclk will be divided by (divx + 2) and how many times it will be divided by (divx + 3), as per the formula shown in 60a8h above. when 001h, mclk is divided by (divx + 2) once, then divided 4095 times by (divx + 3). note: 0 is an illegal value for divxn (same ratio as 1) reserved 15:12 r/w reserved. should be written as 0000. table 69 - srts transmit gapping divider register address: 60b0(hex) label: srtgd reset value: 0000 (hex) label bit position type description tx_gapping 7:0 r/w this field provides the separation between consecutive pulses of the f b clock. this field should be set according to the following formula: (256 / number of channels per vc) - 1. the result must be rounded down. 1 channel -> 255 2 channels -> 127 3 channels -> 84 ... tx_ch_per_vc 14:8 r/w number of channels in the vc that is selected for transmitting the srts. 0h -> 1 channel 1h -> 2 channels ... 79h -> 122 channels note: since maximum number of channels per vc is 122, values 7a:7f are reserved. reserved 15 r/w reserved. should be written as 0. rxvclkavg mclk 1 divx 2 + () divxn () divx 3 + () 4096 divxn C () + 4096 ------------------------------------------------------------------------------------------------------------------------------- ---------- - ------------------------------------------------------------------------------------------------------------------------------- ----------- =
mt90500 110 table 70 - srts transmit byte counter register address: 60b2(hex) label: srtbc reset value: 0177 (hex) label bit position type description byte number 8:0 r/w number of tdm payload bytes in eight (8) consecutive cells. for pointerless aal1 structured data transfer (i.e. n=1 sdt), this value is 376. for aal1 sdt (n not equal to 1), this value is normally 375 (although it may be 374, or 372, depending on the number of p-bytes sent in each 8-cell sequence). reserved 15:9 r/o always read 0000_000 table 71 - srts receive gapping divider register address: 60b4(hex) label: srrgd reset value: 0000 (hex) label bit position type description rx_gapping 7:0 r/w this field provides the separation between consecutive pulses of the f b clock. this field should be set according to the following formula: (256 / number of channels per vc) - 1. the result must be rounded down. 1 channel -> 255 2 channels -> 127 3 channels -> 84 ... rx_ch_per_vc 14:8 r/w number of channels in the vc that is selected for receiving the srts. 0 -> 1 channel 1 -> 2 channels ... note: since maximum number of channels per vc is 122, values 7a:7f are reserved. reserved 15 r/w reserved. should be written as 0. table 72 - srts receive byte counter register address: 60b6(hex) label: srrbc reset value: 0177 (hex) label bit position type description byte number 8:0 r/w number of tdm payload bytes in eight (8) consecutive cells. for pointerless aal1- structured data transfer (i.e. n=1 sdt), this value is 376. for aal1 sdt (n not equal to 1), this value is normally 375 (although it may be 374, or 372, depending on the number of p-bytes sent in each 8-cell sequence). reserved 15:9 r/o always read 0000_000
mt90500 111 5.2.6 tdm time slot control table 73 - output enable registers address: 7000 + 2n (hex) - n=0,1,2,...,127 label: oem reset value: xxxx (hex) label bit position type description oe 15:0 r/w output enable for 16 time slots - when high, these bits enable the corresponding time slots to be driven onto the tdm bus. <0> oe for stream 0 <1> oe for stream 1 <2> oe for stream 2 ........ <14> oe for stream 14 <15> oe for stream 15 each register represents a particular time slot (e.g. 7000h => time slot 0; 70feh => time slot 127). within each register, the individual bits correspond to the st-bus streams, as listed above.
mt90500 112 6. electrical specification 6.1 dc characteristics * exceeding these figures may cause permanent damage. functional operation under these conditions is not guaranteed. voltage measurements are with respect to ground (v ss ) unless otherwise stated. a. typical ?gures are at 25 c and are for design aid only; not guaranteed and not subject to production testing. voltage measurements are with respect to ground (v ss ) unless otherwise stated. table 74 - absolute maximum ratings parameter symbol min max units 1 supply voltage - 5 volt rail v dd5 - 0.3 6.5 v 2 supply voltage - 3.3 volt rail v dd3 - 0.3 3.9 v 3 voltage on any i/o pin (except tristate) v i/o v ss - 0.5 v dd5 + 0.3 v 4 voltage on tristate pin v i/o3 v ss - 0.5 v dd3 + 0.3 v 5 continuous current at digital inputs i in 10 ma 6 continuous current at digital outputs i o 24 ma 7 storage temperature t s - 40 + 125 c 8 package power dissipation (pqfp) pd 4 w table 75 - recommended operating conditions characteristics sym min typ a max units test conditions 1 operating temperature t op - 40 + 85 c 2 supply voltage, 5 volt rail v dd5 4.75 5.0 5.25 v 3 supply voltage, 3.3 volt rail v dd3 3.13 3.3 3.46 v 4 input voltage low - all inputs v ss 0.4 v 5 input voltage high - ttl & 3v cmos inputs 2.4 v dd5 v 6 input voltage high - tristate input 2.4 3.6 v v dd3 = 3.3 v table 76 - dc characteristics characteristics sym min typ a max units test conditions b 1 supply current - 3.3 v supply i dd3 400 500 ma 60 mhz, outputs unloaded 2 supply current - 5 v supply i dd5 1 ma outputs unloaded 3 input high voltage (3v cmos) v ihc 0.7 x v dd3 2.3 v 4 input low voltage (3v cmos) v ilc 0.7 0.2 x v dd3 v 5 switching threshold (3v cmos) v tc 0.5 x v dd3 v 6 input high voltage (ttl) v ih 2.0 5.5 v 7 input low voltage (ttl) v il v ss - 0.5 0.8 v 8 switching threshold (ttl) v tt 1.4 2.0 v 9 schmitt trigger positive threshold v t+ 1.7 2.0 v 10 schmitt trigger negative threshold v t- 0.8 1.0 v 11 schmitt trigger hysteresis v th 0.6 0.7 v 12 differential input high voltage v ihd + 0.5 v clkx2pi - clkx2ni
mt90500 113 precautions during power sequencing latch-up is not a concern during power sequencing. there is no requirement for sequencing 3.3 v and 5 v supplies during power up. however, to minimize over-voltage stress during system start-up, the 3.3 v supply applied to the mt90500 should be brought to a level of at least vdd = 3.0 v before a signal line is driven to a level greater than or equal to 3.3 v. this practice can be implemented either by ensuring that the 3.3 v power turns on simultaneously with or before the system 5 v supply turns on, or by ensuring that all 5 v signals are held to a logic low state during the time that vdd < 3.0 v. regardless of the method chosen to limit over- voltage stress during power up, exposure must be limited to no more than + 6.5 v input voltage (v in ). the trist a te pin of the mt90500 can be asserted low on power-up to prevent bus contention. precautions during power failure latch-up is not a concern in power failure mode. although extended exposure of the mt90500 to 5 v signals during 3.3 v supply power failure is not recommended, there are no restrictions as long as v in does not exceed the absolute maximum rating of 6.5 v. to minimize over-voltage stress during a 3.3 v power supply failure, the designer should either link the power supplies to prevent this condition or ensure that all 5 v signals connected to the mt90500 are held in a logic low state until the 5 v supply is deactivated. pull-ups pull-ups from the 5v rail to 3.3v (5v tolerant) outputs of the mt90500 can cause reverse leakage currents into those 3.3v outputs when they are active high. (no signi?cant reverse current is present during the high impedance state.) if the application can put the mt90500 in a state where mclk is stopped, and a large number of 3.3v output buffers are held in a static high state, current can ?ow from the 5v rail to the 3.3v rail. if this mclk-stopped state can not be avoided, the user should determine if the total mt90500 reverse current will have a negative impact on the system 3.3v power supply. alternatively, the trist a te pin of the mt90500 can be asserted low to put all outputs in the high impedance state. a. typical ?gures are at 25 c and are for design aid only; not guaranteed and not subject to production testing. b. t op = -40 c to 85 c; v dd5 = 5v 5%; v dd3 = 3.3v 5% voltage measurements are with respect to ground (v ss ) unless otherwise stated. 13 differential input low voltage v ild - 0.5 v clkx2pi - clkx2ni 14 input leakage current inputs with pull-down resistors inputs with pull-up resistors i il / i ih 1 10 m av in = v ddx or v ss i ih 69 124 190 m av in = v dd5 i il - 70 - 142 - 225 m av in = v ss 15 input pin capacitance c i 10 pf 16 output high voltage v oh 2.4 3.3 v ddx vi oh = rated current (4 or 12 ma) 17 output low voltage v ol 0.2 0.4 v i ol = rated current (4 or 12 ma) 18 high impedance leakage i oz -10 1.0 +10 m av o = v ss or v dd 19 output pin capacitance c o 10 pf table 76 - dc characteristics characteristics sym min typ a max units test conditions b
mt90500 114 6.2 ac characteristics 6.2.1 main tdm bus table 77 - main tdm bus output clock parameters characteristic sym min typ max units test conditions clock skew - clkx2po falling to clkx1 change t sk 10 ns c l = 50 pf 20 ns c l = 200 pf clkx2po - output clock period 2.048 mbps bus (4.096 mhz clock) 4.096 mbps bus (8.192 mhz clock) 8.192 mbps bus (16.384 mhz clock) t cx2p 244 122 61 ns ns ns clkx2po pulse width (high / low) 2.048 mbps bus (4.096 mhz clock) 4.096 mbps bus (8.192 mhz clock) 8.192 mbps bus (16.384 mhz clock) t cx2h/l 118 57 26.5 122 61 30.5 126 65 34.5 ns ns ns 16.39 mhz (61 ns) input clock with 50/50 duty cycle . clkx1 - output clock period 2.048 mbps 4.096 mbps 8.192 mbps t cx1p 488 244 122 ns ns ns clkx1 pulse width (high / low) 2.048 mbps 4.096 mbps 8.192 mbps t cx1h/l 240 118 57 244 122 61 248 126 65 ns ns ns 16.39 mhz (61 ns) input clock . frame pulse width positive frame pulse - 2.048 mbps negative frame pulse - 2.048 mbps positive frame pulse - 4.096 mbps negative frame pulse - 4.096 mbps positive frame pulse - 8.192 mbps negative frame pulse - 8.192 mbps t fpw 488 244 244 122 122 61 ns ns ns ns ns ns 16.39 mhz (61 ns) input clock . frame pulse delay positive: clkx2po falling to fsync rising negative: clkx2po rising to fsync falling t fpd 0 -2 10 20 ns ns c l = 50 pf c l = 200 pf 0 -2 10 20 ns ns c l = 50 pf c l = 200 pf v tt clkx2po sti/o v tt figure 39 - nominal tdm bus timing clkx1 bit 0, last channel bit 1, last channel v tt bit 6, channel 0 bit 7, channel 0 fsync (neg.) v tt v tt fsync (pos.)
mt90500 115 note: some scsa devices may require a wider frame pulse at 4 mbps and at 8 mbps than the mt90500 provides. also, h-mvip uses a 488 ns wide frame pulse at 8 mbps. v tt v tt v tt v tt fsync clkx2po t fpw sto figure 40 - main tdm bus output clocking parameters - positive frame pulse clkx1 t sodd bit 7, channel 0 bit 1, last channel bit 0, last channel t cx1l t cx1h t cx1p t cx2l t cx2h t cx2p t fpd bit 5, channel 0 t sk bit 6, channel 0 v tt v tt v tt fsync clkx2po t fpw sto t cx2h t cx2l t cx2p v tt figure 41 - main tdm bus output clocking parameters - negative frame pulse clkx1 bit 0, last channel bit 7, channel 0 bit 6, channel 0 bit 5, channel 0 t fpd t cx1h t cx1l t cx1p t sodd t sk
mt90500 116 table 78 - main tdm bus data output parameters characteristic sym min typ max units test conditions sto delay - data to data change clkx1 rising and (sto high or sto low) to sto change fast bus slow bus t sodx 5 10 ns ns c l = 50 pf c l = 200 pf 5 15 ns ns c l = 50 pf c l = 200 pf sto delay - data to data valid clkx1 rising and (sto high or sto low) to (sto low or sto high) fast bus slow bus t sodd 31 41 ns ns c l = 50 pf c l = 200 pf 52 62 ns ns c l = 50 pf c l = 200 pf drive to high-z clkx1 rising and sto valid to sto high-z fast bus slow bus t sodz 20 20 ns ns c l = 200 pf high-z to drive clkx1 rising and sto high-z to sto change fast bus slow bus t sozx 5 10 ns ns c l = 200 pf high-z to data valid clkx1 rising and sto high-z to sto valid fast bus slow bus t sozd 41 62 ns ns c l = 200 pf v tt v tt v tt figure 42 - main tdm bus - serial output timing clkx1 sto1 valid data valid data valid data valid data t sodx t sodd sto2 valid data high-z valid data t sodz t sozx high-z t sozd
mt90500 117 table 79 - main tdm bus input clock parameters characteristic sym min typ max units test conditions clock skew - clkx2 falling to clkx1 change t fsk 10 ns clkx2 - input clock period 2.048 mbps bus (4.096 mhz clock) 4.096 mbps bus (8.192 mhz clock) 8.192 mbps bus (16.384 mhz clock) t cx2p 244 122 61 ns ns ns clkx2 input pulse width (high / low) 2.048 mbps bus (4.096 mhz clock) 4.096 mbps bus (8.192 mhz clock) 8.192 mbps bus (16.384 mhz clock) t cx2h/l 97.6 48.8 26.2 122 61 30.5 146.4 73.2 34.8 ns ns ns 16.39 mhz (61 ns) input clock with 50/50 duty cycle . clkx1 - input clock period 2.048 mbps 4.096 mbps 8.192 mbps t cx1p 488 244 122 ns ns ns clkx1 pulse width (high / low) 2.048 mbps 4.096 mbps 8.192 mbps t cx1h/l 195.2 97.6 48.8 244 122 61 292.8 146.4 73.2 ns ns ns 16.39 mhz (61 ns) input clock . pllclk - input clock period 16.384 mhz t pll 61 ns pllclk pulse width (high / low) 16.384 mhz t pllh/l 26.2 30.5 34.8 ns frame pulse setup time fsync valid to clkx2 falling (tclksyn = 1) fsync valid to clkx1 rising (negative fsync) fsync valid to clkx1 falling (positive fsync) t fis 5 5 5 ns mt90500 is tdm timing bus slave. frame pulse hold time clkx2 falling to fsync invalid (tclksyn = 1) clkx1 rising to fsync invalid (negative fsync) clkx1 falling to fsync invalid (positive fsync) t fih 10 10 10 ns mt90500 is tdm timing bus slave. table 80 - main tdm bus input data parameters characteristic sym min typ max units test conditions sti setup time - sti valid to clkx1 falling 2/4 sampling t sis 5ns sti hold time - clkx1 falling to sti invalid 2/4 sampling t sih 10 ns sti setup time - sti valid to clkx2 rising 3/4 sampling t sis 5ns sti hold time - clkx2 rising to sti invalid 3/4 sampling t sih 10 ns sti setup time - sti valid to clkx1 rising 4/4 sampling t sis 5ns sti hold time - clkx1 rising to sti invalid 4/4 sampling t sih 10 ns
mt90500 118 v tt v tt fsync clkx2 sti v tt v tt figure 43 - main tdm bus - 2/4 sampling clkx1 t sis t sih bit 5, channel 0 bit 6, channel 0 bit 0, last channel bit 1, last channel bit 7, channel 0 v tt sto bit 7, channel 0 bit 1, last channel bit 0, last channel bit 5, channel 0 bit 6, channel 0 t fis t fih v tt fsync clkx2 sti v tt v tt figure 44 - main tdm bus - 3/4 sampling clkx1 v tt t sis t sih bit 5, channel 0 bit 6, channel 0 bit 0, last channel bit 1, last channel bit 7, channel 0 v tt sto bit 7, channel 0 bit 1, last channel bit 0, last channel bit 5, channel 0 bit 6, channel 0 t fis t fih
mt90500 119 v tt v tt fsync clkx2 sti v tt v tt figure 45 - main tdm bus - 4/4 sampling clkx1 t sis t sih bit 6, channel 0 bit 0, last channel bit 1, last channel bit 7, channel 0 v tt sto bit 7, channel 0 bit 1, last channel bit 0, last channel bit 5, channel 0 bit 6, channel 0 t fis t fih
mt90500 120 6.2.2 local tdm bus table 81 - local tdm bus clock parameters characteristic sym min typ max units test conditions clock skew - locx2 falling to locx1 change t lsk 10 ns c l = 50 pf locx2 period t lx2p 244 ns locx2 pulse width (high / low) t lx2h/l 119 122 125 ns input clock = 16.39 mhz (61 ns) locx1 period t lx1p 488 ns locx1 pulse width (high / low) t lx1h/l 241 244 247 ns frame pulse width positive frame pulse negative frame pulse t lsw 488 244 ns ns frame pulse delay positive: locx2 falling to lsync rising negative: locx2 rising to lsync falling t lsd 0 0 10 10 ns ns c l = 50 pf frame pulse guaranteed setup positive: lsync rising to locx2 falling negative: lsync falling to locx2 falling t lss 220 98 ns ns input clock = 16.39 mhz (61 ns) c l = 50 pf frame pulse guaranteed hold positive: locx2 falling to lsync falling negative: locx2 falling to lsync rising t lsh 230 108 ns ns input clock = 16.39 mhz (61 ns) c l = 50 pf note: the local bus operates at 2.048 mbps only. table 82 - local tdm bus data output parameters characteristic sym min typ max units test conditions locsto delay - data to data change locx1 rising and ((locsto high to locsto low) or (locsto low to locsto high)) t lodx 5nsc l = 50 pf locsto delay - data to data valid locx1 rising and ((locsto high to locsto low) or (locsto low to locsto high)) t lodd 60 ns c l = 50 pf note 1: the local bus output is never high impedance, as data is always driven out on locsto. note 2: there is no differentiation between fast bus and slow bus on the local bus.
mt90500 121 v tt lsync locx2 t lsw locsto v tt v tt figure 46 - local tdm bus output parameters - positive frame pulse locx1 t lodd bit 7, channel 0 bit 1, last channel bit 0, last channel v tt t lx1l t lx1h t lx1p t lx2l t lx2h t lx2p t lsd bit 5, channel 0 t lsk t lss t lsh bit 6, channel 0 t lodx v tt lsync locx2 t lsw locsto t lx2h t lx2l t lx2p v tt v tt figure 47 - local tdm bus output parameters - negative frame pulse locx1 bit 0, last channel bit 7, channel 0 bit 6, channel 0 bit 5, channel 0 v tt t lsd t lx1h t lx1l t lx1p t lodd t lsk t lsh t lss t lodx
mt90500 122 table 83 - local tdm bus data input parameters characteristic sym min typ max units test conditions locsti setup time - locsti valid to locx1 falling 2/4 sampling t lis 10 ns locsti hold time - locx1 falling to locsti invalid 2/4 sampling t lih 10 ns locsti setup time - locsti valid to locx2 rising 3/4 sampling t lis 10 ns locsti hold time - locx2 rising to locsti invalid 3/4 sampling t lih 5ns locsti setup time - locsti valid to locx1 rising 4/4 sampling t lis 10 ns locsti hold time - locx1 rising to locsti invalid 4/4 sampling t lih 5ns v tt lsync locx2 locsti v tt v tt figure 48 - local tdm bus - positive frame pulse, 2/4 sampling locx1 v tt t lis t lih bit 5, channel 0 bit 6, channel 0 bit 0, last channel bit 1, last channel bit 7, channel 0 v tt locsto bit 7, channel 0 bit 1, last channel bit 0, last channel bit 5, channel 0 bit 6, channel 0
mt90500 123 v tt lsync locx2 locsti v tt v tt figure 49 - local tdm bus - negative frame pulse, 3/4 sampling locx1 v tt t lis t lih bit 5, channel 0 bit 6, channel 0 bit 0, last channel bit 1, last channel bit 7, channel 0 v tt locsto bit 7, channel 0 bit 1, last channel bit 0, last channel bit 5, channel 0 bit 6, channel 0 v tt lsync locx2 locsti v tt v tt figure 50 - local tdm bus - negative frame pulse, 4/4 sampling locx1 v tt t lis t lih bit 6, channel 0 bit 0, last channel bit 1, last channel bit 7, channel 0 v tt locsto bit 7, channel 0 bit 1, last channel bit 0, last channel bit 5, channel 0 bit 6, channel 0
mt90500 124 6.2.3 cpu interface - accessing registers and external memory table 84 - intel microprocessor interface timing - read cycle parameters characteristic sym min typ max units test conditions address setup - (aem and a[15:1] valid) to ( cs and rd asserted) t adds 0ns address hold - (cs or rd de- asserted) to (aem and a[15:1] invalid) t addh 0ns rdy de-asserted - ( cs and rd asserted) to rdy de-asserted t rdy 21 ns 1) ~ 1 mclk cycle + 4 ns 2) c l = 50 pf rdy delay - ( cs and rd asserted) to rdy asserted t rdyd 100 360 1000 ns 1) 6 mclk < t rdyd < 60 mclk 2) c l = 50 pf data output setup - d[15:0] valid to rdy asserted t ds 15 ns 1) ~ 1 mclk cycle - 1 ns 2) c l = 50 pf data output hold - ( cs or rd de- asserted) to d[15:0] invalid t dh 315ns 1) min. measurement is to d[15:0] invalid; max. measurement is to d[15:0] high-impedance 2) c l = 50 pf note 1: mclk = 60 mhz (16.6 ns). note 2: both cs and rd must be asserted for a read cycle to occur. a read cycle is completed when either cs or rd is de-asserted. note 3: there should be a minimum of 4 mclk periods between cpu accesses, to allow the mt90500 to recognize the accesses as separate. rd v tt figure 51 - intel cpu interface timing - read access cs wr v tt v tt a[15:1] aem v tt address valid t adds t addh v tt rdy t rdy t rdyd d[15:0] v tt data valid t dh t ds
mt90500 125 table 85 - intel microprocessor interface timing - write cycle parameters characteristic sym min typ max units test conditions address setup - (aem and a[15:1] valid) to ( cs and wr asserted) t adds 0ns address hold - ( cs or wr de- asserted) to (aem and a[15:1] invalid) t addh 0ns rdy de-asserted - ( cs and wr asserted) to rdy de-asserted t rdy 21 ns 1) ~ 1 mclk cycle + 4 ns 2) c l = 50 pf rdy delay - ( cs and wr asserted) to rdy asserted t rdyd 100 415 1000 ns 1) 6 mclk < t rdyd < 60 mclk 2) c l = 50 pf write cycle hold time - rdy asserted to ( cs or wr de-asserted) t wrh 0ns data input setup - d[15:0] valid to ( cs and wr asserted) t ds 0ns data input hold - ( cs or wr de- asserted) to d[15:0] invalid t dh 0ns note 1: mclk = 60 mhz (16.6 ns). note 2: both cs and wr must be asserted for a write cycle to occur. a write cycle is completed when either cs or wr is de-asserted. note 3: there should be a minimum of 4 mclk periods between cpu accesses, to allow the mt90500 to recognize the accesses as separate. wr v tt figure 52 - intel cpu interface timing - write access cs rd t wrh v tt v tt a[15:1] aem v tt address valid t adds t addh v tt rdy t rdy t rdyd d[15:0] v tt data valid t dh t ds
mt90500 126 table 86 - motorola microprocessor interface timing - read cycle parameters characteristic sym min typ max units test conditions address setup - (r/ w, aem and a[15:1] valid) to ( cs and ds asserted) t adds 0ns address hold - ( cs or ds de- asserted) to (aem, a[15:1] and r/ w invalid) t addh 0ns dtack high - ( cs and ds asserted) to dtack driving one t dtk1 34 ns 1) ~ 2 mclk cycles 2) c l = 50 pf dtack delay - ( cs and ds asserted) to dtack asserted t dtkd 100 375 1000 ns 1) 6 mclk < t rdyd < 60 mclk 2) c l = 50 pf data to dtack delay - d[15:0] valid to dtack asserted t ddtk 14 ns 1) ~ 1 mclk cycle - 2 ns 2) c l = 50 pf dtack hold - ( cs or ds de-asserted) to dtack driving high t dtkh 515ns c l = 50 pf dtack high-impedance - ( cs or ds de-asserted) to dtack high- impedance t dtkz 620ns c l = 50 pf data output hold - ( cs or ds de- asserted) to d[15:0] invalid t dh 315ns 1) min. measurement is to d[15:0] invalid; max. measurement is to d[15:0] high-impedance 2) c l = 50 pf note 1: mclk = 60 mhz (16.6 ns). note 2: both cs and ds must be asserted for a read cycle to occur. a read cycle is completed when either cs or ds is de-asserted. note 3: there should be a minimum of 4 mclk periods between cpu accesses, to allow the mt90500 to recognize the accesses as separate. v tt ds v tt figure 53 - motorola cpu interface timing - read access cs dt a ck v tt a[15:1] aem v tt address valid t adds t addh v tt r/ w d[15:0] v tt data valid t dh t addh t ddtk t dtk1 t dtkd t dtkh t dtkz
mt90500 127 table 87 - motorola microprocessor interface timing - write cycle parameters characteristic sym min typ max units test conditions address setup - (r/ w, aem and a[15:1] valid) to ( cs and ds asserted) t adds 0ns address hold - ( cs or ds de-asserted) to (aem, a[15:1] and r/ w invalid) t addh 0ns dtack high - ( cs and ds asserted) to dtack driving one t dtk1 34 ns 1) ~ 2 mclk cycles 2) c l = 50 pf dtack delay - ( cs and ds asserted) to dtack asserted t dtkd 100 420 1000 ns 1) 6 mclk < t rdyd < 60 mclk 2) c l = 50 pf dtack hold - ( cs or ds de-asserted) to dtack driving high t dtkh 515ns c l = 50 pf dtack high-impedance - ( cs or ds de-asserted) to dtack high-impedance t dtkz 620ns c l = 50 pf data input setup - d[15:0] valid to ( cs and ds asserted) t ds 0ns c l = 50 pf data input hold - ( cs or ds de- asserted) to d[15:0] invalid t dh 0ns c l = 50 pf note 1: mclk = 60 mhz (16.6 ns). note 2: both cs and ds must be asserted for a write cycle to occur. a write cycle is completed when either cs or ds is de-asserted. note 3: there should be a minimum of 4 mclk periods between cpu accesses, to allow the mt90500 to recognize the accesses as separate. v tt ds v tt figure 54 - motorola cpu interface timing - write access cs dt a ck v tt a[15:1] aem v tt address valid t adds t addh v tt r/ w t ds d[15:0] v tt data valid t dh t addh t dtk1 t dtkd t dtkh t dtkz
mt90500 128 6.2.4 interface with external memory table 88 - mclk - master clock input parameters characteristic sym min typ max units test conditions mclk frequency t mf 60 60.006 mhz mclk period t mp 16.7 ns mclk pulse width (high / low) t mh/l 7.5 8.33 ns table 89 - external memory interface timing - clock parameters characteristic sym min typ max units test conditions memclk period t memp 16.7 ns memclk = mclk = 60 mhz memclk pulse width (high / low) t memh/ l 7.6 8.33 9.1 ns mclk = 16.7 ns period, 50/50 duty cycle 6.7 8.33 10.0 ns mclk = 16.7 ns period, 45/55 duty cycle table 90 - external memory interface timing - read cycle parameters characteristic sym min typ max units test conditions data input setup - (mem_dat[31:0] and mem_par[3:0] valid) to memclk rising t dis 5ns data input hold time - memclk rising to (mem_dat[31:0] and mem_par[3:0] invalid) t dih 1ns output delay - memclk rising to (mem_add[17:0] valid and mem_cs[1:0][h/ l] and mem_wr[3:0] asserted) t od 10 ns c l = 50 pf output hold time - memclk rising to (mem_add[17:0] invalid and mem_cs[1:0][h/l] and mem_wr[3:0] de- asserted) t oh 1.5 ns c l = 50 pf note: mem_oe is continuously asserted low after reset. table 91 - external memory interface timing - write cycle parameters characteristic sym min typ max units test conditions output delay - memclk rising to (mem_add[17:0], mem_dat[31:0] and mem_par[3:0] valid) and ( mem_cs[1:0][h/ l] and mem_wr[3:0] asserted) t od 11 ns c l = 50 pf output hold time - memclk rising to (mem_add[17:0], mem_dat[31:0] and mem_par[3:0] invalid) and ( mem_cs[1:0][h/l] and mem_wr[3:0] de- asserted) t oh 1.5 ns c l = 50 pf high-z to drive time - memclk rising to (mem_dat[31:0] and mem_par[3:0] change) t zd 1nsc l = 50 pf minimum hold in high-z drive to high-z time - memclk rising to (mem_dat[31:0] and mem_par[3:0] high-z) t oz 5ns note: mem_oe is continuously asserted low after reset.
mt90500 129 v tt address1 valid v tt v tt v tt v tt v tt v tt memclk mem_dat[31:0] mem_add [17:0] mem_cs0h/l mem_cs1h/l mem_wr[3:0] mem_oe figure 55 - external memory interface timing - read cycle mem_par[3:0] t od mclk t memp t memh t meml t dis t oh data1 valid t od data2 valid t dih t oh address2 valid
mt90500 130 v tt v tt v tt v tt v tt v tt v tt memclk mem_dat[31:0] mem_add [17:0] mem_cs0h/l mem_cs1h/l mem_wr[3:0] mem_oe figure 56 - external memory interface timing - write cycle mem_par[3:0] t od t od mclk t memp t memh t meml address valid t od t od t oh t oh t oh data valid t oh t zd
mt90500 131 6.2.5 utopia interfaces 6.2.5.1 primary utopia interface table 92 - primary utopia interface parameters - transmit characteristic sym min typ max units test conditions ptxclk period t ptxp 40 ns ptxclk = 25 mhz ptxclk pulse width (high / low) t ptxh/l 16 20 24 ns input setup time - ptxclav valid to ptxclk rising t ptxis 10 ns input hold time - ptxclk rising to ptxclav de-asserted t ptxih 1ns output delay - ptxclk rising to (ptxdata[7:0] valid and ptxen and ptxsoc asserted) t ptxd 20 ns c l = 50 pf output hold time - ptxclk rising to (ptxdata[7:0] invalid and ptxen and ptxsoc de-asserted) t ptxh 1nsc l = 50 pf note 1: the mt90500 operates with the utopia cell-level handshake. note 2: the mt90500 always inserts 1-4 idle cycles between cells on the tx utopia port. v tt ptxsoc ptxclk t ptxh t ptxl t ptxp figure 57 - primary utopia bus - transmit timing v tt ptxen ptxdata[7:0] x h1 h2 h3 x p45 p46 at least 4 cycles before the next cell p47 p48 v tt v tt v tt ptxclav t ptxd t ptxih t ptxis t ptxh t ptxh t ptxh
mt90500 132 table 93 - primary utopia interface parameters - receive characteristic sym min typ max units test conditions prxclk period t prxp 40 ns prxclk = 25 mhz prxclk pulse width (high / low) t prxh/l 16 20 24 ns input setup time - (prxclav, prxen, prxsoc asserted and prxdata[7:0] valid) to prxclk rising t prxis 10 ns input hold time - prxclk rising to (prxdata[7:0] invalid and prxsoc, prxclav, and prxen de- asserted) t prxih 1ns note 1: the mt90500 operates with the utopia cell-level handshake. note 2: the relative timing of prxclav, prxen and prsoc must be as shown, or as given in utopia level 1 version 2.01 figure 6. the timing shown is also valid for applications where prxen is permanently asserted. v tt prxsoc prxclk t prxh t prxl t prxp figure 58 - primary utopia bus - receive timing v tt prxen prxdata[7:0] x x h1 h2 p47 p48 v tt v tt v tt prxclav t prxis t prxih x t prxih t prxih h1
mt90500 133 6.2.5.2 secondary utopia interface table 94 - secondary utopia parameters timing characteristic sym min typ max units test conditions stxclk period t stxp 40 ns stxclk = 25 mhz stxclk pulse width (high / low) t stxh/l 16 20 24 ns input setup time - (stxdata[7:0] valid; stxsoc and stxen asserted) to stxclk rising t stxis 10 ns input hold time - stxclk rising to (stxdata[7:0] invalid and stxsoc and stxen de-asserted) t stxih 1ns output delay - stxclk rising to stxclav asserted t stxd 20 ns c l = 50 pf output hold time - stxclk rising to stxclav de-asserted t stxh 1c l = 50 pf note: the mt90500 requires at least one idle cycle between cells driven into the secondary utopia interface. v tt stxsoc stxclk t stxh t stxl t stxp figure 59 - secondary utopia interface v tt stxen stxdata[7:0] x h1 h2 h3 x p45 p46 at least 4 cycles before the next cell p47 p48 v tt v tt v tt stxclav t stxd t stxis t stxih h1 t stxih t stxih note: stxen must be de-asserted for at least one cycle between cells, as shown here.
mt90500 134 6.2.6 srts user interface 6.2.7 message channel interface table 95 - srts interface parameters characteristic sym min typ max units test conditions srts ena delay - locx1 falling to corsigc asserted t enad 20 ns 1) locx1 = 2.048 mhz (488 ns). 2) c l = 50 pf srts data delay - locx1 falling to corsigd valid t dd 20 ns 1) locx1 = 2.048 mhz (488 ns). 2) c l = 50 pf srts ena hold time - locx1 falling to corsigc de-asserted t enah 0nsc l = 50 pf note: srts is assumed to be sampled on locx1 rising. srts data hold time - locx1 falling to corsigd invalid t dh 0nsc l = 50 pf note: srts is assumed to be sampled on locx1 rising. table 96 - message channel parameters characteristic sym min typ max units test conditions mcclk period t mccp 488 ns mcclk pulse width (high / low) t mcch/l 237 244 252 ns clkx2 period 244 ns, 122 ns or 61 ns. skew - clkx2 falling to mcclk change t mccd 522nsc l = 50 pf transmit delay - mctx to mc mctx falling to mc falling mctx rising to mc high-z t mctdl t mctdz 4 3 16 13 ns c l = 50 pf receive delay - mc to mcrx mc falling to mcrx falling mc rising to mcrx rising t mcrd 4 3 15 14 ns c l = 50 pf v tt corsigd figure 60 - srts user interface timing locx1 (srtsdata) (srtsena) corsigc t enad v tt (srts clock) v tt srts bit 3 t dd t dh srts bit 2 srts bit 1 srts bit 0 t enah
mt90500 135 figure 61 - message channel timing clkx1 (8 mhz) fsync mcclk (2 mhz) clkx1 (4 mhz) clkx1 (2 mhz) clkx2 (fsync not to scale) mc (data) mctx (data in) mcrx (data out) ~ ~ ~ ~ ~ ~ v tt v tt v tt v tt v tt v tt v tt v tt t mccp t mcch t mccl t mccd t mccd t mctdz t mcrd t mcrd t mctdl
mt90500 136 6.2.8 boundary-scan test access interface table 97 - boundary-scan test access port timing parameter symbol min typ max units test conditions tck period width t tclk 100 ns tck period width low t tclkl 40 ns tck period width high t tclkh 40 ns tdi setup time to tck rising t disu 10 ns tdi hold time after tck rising t dih 20 ns tms setup time to tck rising t mssu 10 ns tms hold time after tck rising t msh 20 ns tdo output delay from tck falling t dod 030nsc l = 30 pf trst pulse width t trst 100 ns t mssu tdi tdo tms tck t disu t msh t dih t dod t tclkh t tclkl t tclk trst t trst
mt90500 137 7. applications 7.1 board level applications figure 62 shows a general board level application for the mt90500. this shows a high-level view of the device connection to external memory, a cpu, an atm physical layer device, an atm aal5 sar device, and the tdm backplane.this is a general application diagram; the most frequent variations would be: the number and size of the ssram chips, the type of cpu or phy, the mode of the tdm backplane and tdm local bus (several possibilities are listed in the ?gure), and the presence or absence of a secondary sar. the size of external memory is selected to suit the application, and is tied to the number of tdm 64 kbps channels to be used, the number of vcs to be used, and the cell delay variation tolerance of the receive channels. similarly the cpu and phy are chosen to suit the application. the tdm backplane mode (positive or negative frame-pulse; fast or slow hold time; and 2.048, 4.096, or 8.192 mbps) is application selectable, and the local tdm bus can be enabled for applications which require it (e.g. when it is desirable to have a local hdlc, or dsp, which is not tied to the backplane). the secondary sar may be used in applications which require atm signalling, though it is possible to do a moderate amount of signalling using the tx and rx data fifos in the mt90500, provided that the cpu can perform the rest of the sar functions in software. figure 62 - mt90500 device application block diagram tdm data, clock and sync lines mvip-90 idl st-bus scsa 240-pqfp off-the-shelf sar device (aal5) local memory off-the-shelf atm phy device utopia port external cpu 16-bit cpu port for internal register and external memory pro- gramming h-mvip synchronous sram primary utopia port secondary mt90500
mt90500 138 the mt90500 will work with a variety of standard synchronous sram parts. the burst feature of the synchronous sram is not used by the mt90500, and since the ssram is not connected to a cache controller, some of the control pins of most ssrams are not used by the mt90500. the common control pin names for the ssram, and their connections when used with the mt90500, are listed in table 98, and table 99. the secondary utopia bus of the mt90500, and the transmit utopia multiplexer, allow application ?exibility in working with a variety of off-the-shelf data sars. this feature also allows two mt90500s to be combined for a full 2048 full-duplex tdm channel application (allowing full connection to a 4096 channel backplane). note that each mt90500 carries 1024 channels in each direction, not 2048 transmitted by one mt90500, and 2048 received by the other mt90500. the capabilities of the tx sar and rx sar internal blocks are balanced at 1024 channels. table 98 - mt90500 connections to 18-bit synchronous sram pin function ssram mt90500 notes address a0-a14 mem_add[14:0] data dq[0:7, 9:16] mem_dat[15:0], or mem_dat[31:16] mem_dat[31:16] used for second ssram chip. underrun flag dq[8, 17] mem_par[1:0], or mem_par[3:2] mem_par[3:2] used for second ssram chip. lower byte write enable lw* mem_wr[0], or mem_wr[2] mem_wr[2] used for second ssram chip. upper byte write enable uw* mem_wr[1], or mem_wr[3] mem_wr[3] used for second ssram chip. memory clock k memclk chip enable e* mem_cs0l, or mem_cs0h, or mem_cs1l, or mem_cs1h mem_cs0h used for second ssram chip. mem_cs1x used for second bank of ssram chips. output enable g* mem_oe burst address advance adv* - never enabled - pull to vdd to disable processor address status adsp* - never enabled - pull to vdd to disable controller address status adsc* - always enabled - tie to gnd to enable note: the pin names in this table correspond to those for the motorola 32k x 18-bit burstram synchronous fast static ram (mcm67h518). table 99 - mt90500 connections to 32/36-bit synchronous sram pin function mcm69f536a cy7c1329 mt90500 notes address sa a mem_add data dq dq[31:0] mem_dat[31:0] underrun flag dq8[d:a] (pull-up) mem_par[3:0] if tdm underrun error indication not used, pull- up mem_par[3:0] to v dd3 . byte write sb*[d:a] bw*[3:0] mem_wr[3:0] global write sgw* gw* - tie high (disable global writes) byte write enable sw* bwe* - tie low (enable byte-writes) clock k clk memclk chip enable 1 se1* ce1* - tie low (enable) chip enable 2 se2 ce2 - tie high (enable) chip enable 3 se3* ce3* mem_cs0l mem_cs1l used for second bank/ chip. output enable g* oe* mem_oe burst address advance adv* adv* - tie high (disable) processor address status adsp* adsp* - tie high (disable) controller address status adsc* adsc* - tie low (enable) sleep - zz - tie low burst mode lbo* mode - tie low or tie high no connect - - mem_csxh mem_csxh not used with 32/36 bit memory
mt90500 139 figure 63 shows in greater detail an example of the utopia bus connections when two mt90500 devices and a secondary aal5 sar are used. note that the receive utopia bus is controlled by rxen of the secondary aal5 sar. if the secondary sar is too slow, or con?gured badly, it will throttle-back the cells output by the phy device, and cause lost cells or increased cdv. ( rxen may also be tied low to allow full speed cell reception.) the mt90500 allows the primary utopia port transmit clock (ptxclk) to be one of: the transmit clock of the secondary sar (stxclk), the master clock (mclk) divided by 2 or 4, or an external source. the primary utopia port receive clock (prxclk) is driven by the secondary sar, or it is tied to ptxclk if a secondary sar is not present. prxclk should not be too slow, or cdv may be increased. phy 155mbps device secondary aal5 sar device priority arbitration: leaves remaining bandwidth to upstream device (aal5 sar) round robin arbitration: leaves half+ bandwidth (~78 mbps) to upstream devices (mt90500 and aal5 sar) tx_sar secondary utopia ptxdata[7:0] stxdata[7:0] stxen stxsoc stxclk stxclav stxdata[7:0] tx_sar secondary utopia ptxdata[7:0] prxdata[7:0] prxen prxsoc prxclk prxclav ptxpar ptxen ptxsoc ptxclk ptxclav note: if no secondary sar device is used, ground prxen and tie prxclk to mt90500 ptxclk. primary receive primary transmit primary receive primary transmit ptxpar ptxen ptxsoc ptxclk ptxclav stxen stxsoc stxclk stxclav m u x m u x figure 63 - utopia bus interconnections for two mt90500s and an aal5 sar mt90500 mt90500
mt90500 140 in order to support the multiple sar con?guration shown in figure 63, while remaining utopia level 1 compatible, some utopia pin functions in the mt90500 are expanded. table 100 gives a comparison of the mt90500 to the utopia level 1 standard. also see table 1, primary utopia bus pins, on page 19. table 100 - mt90500 utopia signal directions mt90500 signal name standard utopia signal name mt90500 signal direction standard utopia signal direction notes ptxdata[7:0] txdata[7:0] o atm to phy (atm o) mt90500 acts as atm. ptxsoc txsoc o atm to phy (atm o) ptxen txenb* o atm to phy (atm o) ptxclav txclav i phy to atm (atm i) ptxclk txclk i/o atm to phy (atm o) exception (bidirectional pin allows for external utopia clock source if desired). see main control register on page 84. ptxpar txprty o atm to phy (atm o) prxdata[7:0] rxdata[7:0] i phy to atm (atm i) mt90500 acts as atm. prxsoc rxsoc i phy to atm (atm i) prxen rxenb* i atm to phy (atm o) exception (input allows secondary atm device to control phy). utopia level 1 allows rxenb* to be permanently asserted. prxclav rxclav i phy to atm (atm i) prxclk rxclk i atm to phy (atm o) exception (input allows secondary atm device to drive phy and mt90500). stxdata[7:0] txdata[7:0] i atm to phy (phy i) mt90500 emulates phy. stxsoc txsoc i atm to phy (phy i) stxen txenb* i atm to phy (phy i) stxclav txclav o phy to atm (phy o) stxclk txclk i atm to phy (phy i)
mt90500 141 7.2 system level applications figure 64 depicts an atm adapter card within a work-group hub, switching non-cbr data and cbr voice traf?c with 2 internal switching backplanes (a tdm bus, and a packet bus). the mt90500 device interfaces to the bus transporting cbr traf?c such as voice or video conferencing and the external aal5 sar device interfaces to either a management bus or user data bus such as pci. figure 65 shows a block diagram of the card. figure 66 shows a networking product such as an access concentrator using the mt90500 to perform conversion from tdm links coming out of t1/e1 trunks and the user's internal atm backplane. an external converter might be used to change the mt90500's utopia interface to the user's atm bus. figure 67 shows an application where tdm traf?c must be transported across a proprietary cell bus. the interface chips transform the standard utopia format cells of the mt90500 into the proprietary cell format. figure 68 and figure 69 show how the mt90500 device can be used within a computer telephony integration (cti) system to transport cbr traf?c from multi-stream mvip or scsa buses across an atm link. atm cells aal5 sar atm phy transceiver n x 64 kbps digital trunk card analog or digital set trunk card switch asic data access module switch asic data access module ethernet t.r., atm pstn atm specialized work group ethernet t.r., atm atm switch tdm bus packet bus figure 64 - the mt90500 within a lan hub mt90500
mt90500 142 off-the-shelf atm phy transceiver off-the-shelf aal3/4, aal5 sar st-bus 16 bidirectional tdm streams + clock + 8 khz management or atm 25, 51 and 155 mbps atm cells on primary utopia port atm cells on secondary utopia port figure 65 - using the mt90500 with external sar and atm links in a lan mt90500 user data mitel t1/e1 framers mitel t1/e1 framers mitel pll legacy trunks at 1.5 or 2 mbps st-bus i/f utopia bus utopia to proprietary bus conversion st-bus i/f pcm clocks cell bus on the backplane tdm - atm conversion legacy trunks at 1.5 or 2 mbps figure 66 - access product using internal high speed cell bus on the backplane mt90500
mt90500 143 figure 67 - tdm traf?c transport over a cell bus cell bus atm bus performing cell transport function in a shelf c e l l b u s tdm backplane asynchronous cell bus with no timing transfer mt90500 mt90500 16 x serial tdm streams tdm backplane bus i/f chip line card 16 x serial tdm streams mt90500 mt90500 bus i/f chip line card pc chassis dsp scsi processor dsp conferencing applications utopia phy & optics voice compression circuit mt90810 mt90820 mitel mt90210 pbx atm lan pstn t1/e1 e.g. scsi compressed voice storage compressed video storage e.g. scsi atm 25 or 155 mbps memory mvip/ scsa figure 68 - connecting cti platforms to atm lans atm bus mt90500
mt90500 144 pc chassis video compression circuit atm atm lan pstn t1/e1 atm 25 or 155 mbps pc-atm bus mvip telecom i/f switch fabric atm switch fabric atm switch fabric atm switch fabric utopia figure 69 - the go-mvip, pc-atm bus standard architecture phy & optics utopia atm bus mt90500
mt90500 145 7.3 tdm clock recovery applications 7.3.1 general by the nature of its function - carrying isochronous traf?c over asynchronous transfer mode networks - the mt90500 is used in applications which require some level of synchronization of the tdm clocks at the two ends of the link. further, these applications often require the transfer, or recovery, of the isochronous tdm timing using the atm link. there are several approaches to tdm clock synchronization, both standardized and not- standardized. these clock synchronization methods include: ? plesiochronous - where the atm link is not required to carry timing information, as the timing at both ends is obtained from plesiochronous trunks (perhaps separate public tdm network trunks); ? synchronous, or physical layer - where the timing for both ends is derived from the atm physical link clock; ? adaptive - where timing is carried end-to-end via the atm cell stream; ? srts - a standardized method where timing is carried via time stamps in the atm cell stream, against the atm physical link clock; ? freerun - where no clock synchronization is used at all. the choice of clock synchronization method is dependent upon the application. most standards documents which deal with this issue specify that the recovered clock should be synchronized to the most accurate clock available. the itu-t recommendation i.363.1 provides some guidance on these issues; see the convergence sublayer section, especially source clock frequency recovery method, and appendix ii. the reader is also directed to the mitel semiconductor application note in this topic. 7.3.2 srts clock recovery considerations the srts (synchronous residual time stamp) method uses the csi bit in the aal1 byte to carry time stamp information over the atm data link. figure 70 shows a generic srts application. at the source end, the rts (residual time stamp) is generated by comparing a divided-down atm network clock f nx to a tdm service clock f s . (the tdm service clock f s is generated internally to the mt90500.) the rts is transmitted, once every 8-cell sequence, to the far end. using the common atm network clock (synchronous f nx ) and the rts, the far end can recover the tdm clock. implementation details are given in section 4.6.2, srts clock recovery description, on page 72. note that in order to implement srts clock recovery properly, both the timing source and the far end node must share a common reference atm network clock. if a different atm network clock is present at either end, the recovered tdm clocks will be inaccurate in proportion to the difference in the two atm network clocks. where the atm network clocks are not synchronous, or where it is not known if the atm network clocks are synchronous, adaptive clock recovery can often be used. since the mt90500 is a backplane device, it must work with a ?xed clock rate of 2.048 mhz, 4.096 mhz or 8.192 mhz, rather than the service clock rate carried by the srts link, as given in itu-t recommendation i.363.1. the srts transmit divider (see figure 33) constructs the service clock from the tdm bus clocks. due to internal sampling in the mt90500, there are certain values of tdm-channels-per-vc that are not recommended for the vc carrying the srts information. these are listed in table 101. if a clock slower than 60 mhz is being used for mclk, the designer should note that fnxi must be less than one-third the rate of mclk. table 101 - recommended tdm channel numbers for srts vcs number of tdm channels carried by the srts vc recommended 1, 2, 3, 4, 5, 6, 8, 10, 12, 15, 16, 20, 24, 25, 30, 32, 40, 45, 48, 50, 60, 64, 75, 80, 90, 96 reduced accuracy 7, 9, 11, 13, 14, 17, 18, 21, 23, 28, 36, 51, 85 not recommended 19, 22, 26, 27, 29, 31, 33, 34, 35, 37, 38, 39, 41, 42, 43, 44, 46, 47, 49, 52, 53, 54, 55, 56, 57, 58, 59, 61, 62, 63, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 76, 77, 78, 79, 81, 82, 83, 84, 86, 87, 88, 89, 91, 92, 93, 94, 95
mt90500 146 another consideration in the application of srts clock recovery using the mt90500 is the 5 rts buffer in the receive srts circuitry. this puts an upper limit on the cdv (cell delay variation) of the receive vc carrying srts. each rts in the 5 rts buffer is carried by one 8 cell sequence, and thus represents a ?xed amount of time dependent on the number of tdm channels being carried. table 102 summarizes the maximum cdv supported by the receive srts circuitry at various numbers of tdm channels. 7.3.3 free-running clocks it is usually possible to provide intelligible voice connections using a free-running clock, provided that the crystal accuracy is constrained to a few parts per million. free-running clocks are not recommended however, as relatively frequent frame slips (and accompanying data errors) are inevitable, and this is generally not acceptable for tdm data going to the public network. table 102 - limits on cdv on receive srts vc channels per vc carrying srts time represented by 5 rts (msec) maximum cdv (msec) 1 234 117 2 117 58.6 16 14.7 7.32 24 9.87 4.84 32 7.32 3.66 64 3.66 1.83 96 2.44 1.22 n (general) 125 m sec x 375 / n x 5 = (234 / n) msec 125 m sec x 375 / n x 5 / 2 = (117 / n) msec phy phy 8 khz mca1 tdm timing slave mca1 tdm timing master pll 16.384 mhz tdm bus tdm clocks tdm bus ref8kclk figure 70 - srts clocking application tdm reference atm switch port 1 port 2 cpu f nx f nx 1. mca1 compares f nx to tdm clocks, and generates srts. 4. network down-link carries atm network clock, and srts information. or fpga 6. cpu or fpga runs clock recovery algorithm, based on srts difference. srts difference 5. mca1 generates local srts from f nx and local tdm clocks, and calculates srts difference. clock control 3. the two physical ports must have synchronous physical atm network clocks. 2. network up-link carries atm net- work clock in one direction, and srts information in the other direction. utopia bus utopia bus
mt90500 147 7.4 external memory space and bandwidth calculations 7.4.1 external memory space requirements this section provides a list of the control and data structures used by the mt90500 which are located in external memory. an estimation of the structure size is provided, assuming various scenarios: 256, 512, and 1024 tdm channels in both directions and from 16 to 1024 vcs. (in line with accepted usage for memory, here 1 kbyte = 1024 bytes.) t ransmit memor y requirements refer to figure 19, overview of cbr data transmission process, on page 54. a. tx circular buffer control structure two bytes of ram are required for every tdm channel transmitted. ? 256 tdm channels 0.5 kbyte ? 512 tdm channels 1 kbyte ? 1024 tdm channels 2 kbytes b. transmit circular buffers 64 bytes of ram are required for every tdm channel transmitted. ? 256 tdm channels 16 kbytes ? 512 tdm channels 32 kbytes ? 1024 tdm channels 64 kbytes c. transmit event scheduler assume either 1 scheduler, or all 3 schedulers in service. assume the schedulers are composed of 47 frames (aal1-sdt) and each frame contains 16 two-byte vc pointer entries. ? 1 scheduler ~ 1.5 kbytes ? 3 schedulers ~ 4.4 kbytes d. transmit control structure each control structure begins with 12 bytes of control data, followed by 2 bytes of information for each tdm channel. all transmit control structures occupy an integer number of 16-byte blocks. ? 16 vcs (16 tdm channels per vc) 0.75 kbyte (16 * roundup(12 + 16 * 2) = 768 bytes) ? 128 vcs (4 tdm channels per vc) 4 kbytes (128 * roundup(12 + 4 * 2) = 4096 bytes) ? 1024 vcs (1 tdm channel per vc) 16 kbytes (1024 * roundup(12 + 1 * 2) = 16384 bytes) e. transmit data cell fifo holding 64 cells (refer to section 4.3.3.) ? 64 data cell structures at 64 bytes each 4 kbytes sub-total external memory space requirements to support the tdm to atm transmit process: minimum requirements (256 channels, 1 scheduler): 22.7 kbytes maximum requirements (1024 channels, 3 schedulers): 90.4 kbytes receive memor y requirements see figure 30, overview of cbr data reception process, on page 69. a. vc look-up table note: these numbers assume one-to-one mapping of look-up table entries to vcs. larger sparse tables may be used in some applications, up to 128 kbytes.
mt90500 148 ? 16 possible vcs 0.0625 kbyte ? 128 possible vcs 0.5 kbytes ? 1024 possible vcs 4 kbytes b. rx_sar control structures each control structure begins with 12 bytes of control data, and is then followed by 2 bytes of information for each tdm channel. for the purposes of these calculations, all rx_sar control structures are designed to occupy an integer number of 16-byte blocks. ? 16 vcs (16 tdm channels per vc) 0.75 kbyte (16 * roundup(12 + 16 * 2) = 768 bytes) ? 128 vcs (4 tdm channels per vc) 4 kbytes (128 * roundup(12 + 4 * 2) = 4096 bytes) ? 1024 vcs (1 tdm channel per vc) 16 kbytes (1024 * roundup(12 + 1 * 2) = 16384 bytes) c. receive circular buffers a 64-byte buffer provides 8 ms of buffering capability (1 byte = 125 m s) while a 1024-byte buffer provides up to 128 ms of buffering. in this example, we give sizes for a 64-byte and a 1024-byte (64 / 1024) buffer for each channel. ? 256 tdm channels 16 / 256 kbytes ? 512 tdm channels 32 / 512 kbytes ? 1024 tdm channels 64 / 1024 kbytes d. external memory to internal tdm memory structure four bytes of ram are required for every tdm channel transmitted. ? 256 tdm channels 1 kbyte ? 512 tdm channels 2 kbytes ? 1024 tdm channels 4 kbytes e. receive data cell fifo holding 64 cells (refer to section 4.5.4.) ? 64 at 64 bytes each 4 kbytes sub-total external memory space requirements to support the atm to tdm receive process: minimum requirements (256 channels, 64-byte buffers): ~22 kbytes maximum requirements (1024 channels, 1024-byte buffers): 1052 kbytes t otal memor y requirements total external memory size requirements to support both the tdm to atm transmit process and the atm to tdm receive process: minimum requirements: 44.7 kbytes (256 x 64 kbps bidirectional channels with 16 vcs) maximum requirements: 1142.4 kbytes (1024 x 64 kbps bidirectional channels with 1024 vcs) where the memory requirements are close to the physical size of the provisioned memory, the designer should pay special attention to what memory address boundaries some structures may not cross. (see section 7.4.2.)
mt90500 149 7.4.2 memory structure summary table 103 - summary of external memory structures external memory structure size (in bytes) start on boundary do not cross boundary notes tx circular buffer control structure min: 256 max: 4096 control structure must start on 512-byte boundary: x0 0000 0000 register 6040h: txcbcsbase = bits<20:9> of tx circular buffer control structure base address. control structures cannot cross an 8192-byte (8k) boundary x0 0000 0000 0000 therefore, to ensure that structure never crosses this boundary, start structure on a boundary equal to the structure size. structure size = # of entries * 2 bytes/entry. tx circular buffers 64 (per tdm channel transmitted) first buffer must start on a 512-byte boundary: x0 0000 0000 register 6044h: txcbbase = bits<20:9> of tx circular buffer base address. each subsequent buffer automatically starts on next 64-byte boundary. transmit control structures min: 14 max: 256 (per vc) each control structure must start on a 16-byte boundary: x 0000 register 2040h: txbase = bits<20:16> of transmit control structure base address. the address in the scheduler provides bits<15:4> of address. control structures cannot cross a 256-byte boundary x 0000 0000 transmit event schedulers min: 16 max: 16k (per scheduler - up to 3 can be con?gured) each scheduler must start on a 512-byte boundary: x0 0000 0000 register 2010h/2020h/ 2030h: sbase = bits<20:9> of scheduler base address. min. size = 1 frame * 8 entries/frame * 2 bytes/ entry. typ. size = 47 frames * 16 entries/frame * 2 bytes/entry. max. size = 256 frames * 32 entries/frame * 2 bytes/entry. look-up- ta b l e min: 1024 max: 128k the look-up table must start on a boundary equal to the table size = 2^(m+n+2) = #-of-entries * 4 bytes register 401eh: lutbase = bits<20:5> of pointer to start of look-up table. register 4010h: m and n = number of lsbs from vpi and vci, respectively, to be used in address. min. size = 2^(8 + 2) = 1024. max. size = 2^(15 + 2) = 131072 = 128k. requires external memory allocation of 2^(m + n + 2) bytes.
mt90500 150 external memory to internal memory control structure min: 512 max: 8192 control structure must start on 512-byte boundary: x0 0000 0000 register 6042h: eimcsbase = bits<20:9> of external to internal memory control structure base address. control structures cannot cross an 8192-byte (8k) boundary x0 0000 0000 0000 therefore, to ensure that structure never crosses this boundary, start structure on a boundary equal to the structure size. structure size = # of entries * 4 bytes/entry. rx circular buffers min: 64 max: 1024 (one buffer per received tdm channel) buffers must start on boundary equal to buffer size : 64 - x00 0000 128 - x000 0000 256 - x 0000 0000 512- x0 0000 0000 1024 - x00 0000 0000 number of unique bits provided differs in external to internal memory control structure: 64 bytes - bits<20:6> 128 bytes - bits<20:7> 256 bytes - bits<20:8> 512 bytes - bits<20:9> 1024 bytes - bits<20:10> buffer size is controlled by the external to internal memory control structure and the rx_sar control structure. rx_sar control structures min: 14 max: 256 (per vc) each control structure must start on a 16-byte boundary: x 0000 register 4000h: rxbase = bits<20:18> of rx_sar control structure base addresses. look-up table entry provides bits<17:4> of address. control structures cannot cross a 256-byte boundary x 0000 0000 transmit data cell fifo min: 1024 max: 8192 fifo must start on a 512- byte boundary: x0 0000 0000 register 2050h: txffbase = bits<20:9> of transmit data cell fifo base address. fifos cannot cross an 8192-byte (8k) boundary x0 0000 0000 0000 therefore, to ensure that fifo never crosses this boundary, start fifo on a boundary equal to the fifos size. each non-cbr cell occupies a 64-byte buffer within the fifo. min. size = 16 cells * 64 bytes/cell. max. size = 128 cells * 64 bytes/cell. may be omitted. receive data cell fifo min: 1024 max: 8192 fifo must start on a 512- byte boundary: x0 0000 0000 register 4020h: rxffbase = bits<20:9> of receive data cell fifo base address. fifos cannot cross an 8192-byte (8k) boundary x0 0000 0000 0000 therefore, to ensure that fifo never crosses this boundary, start fifo on a boundary equal to the fifos size. each non-cbr cell occupies a 64-byte buffer within the fifo. min. size = 16 cells * 64 bytes/cell. max. size = 128 cells * 64 bytes/cell. may be omitted. table 103 - summary of external memory structures external memory structure size (in bytes) start on boundary do not cross boundary notes
mt90500 151 7.4.3 external memory bandwidth requirements the following section provides estimated external memory bandwidth requirements to support the functionality of the mt90500, excluding negligible non-cbr traf?c (i.e. data cells or oam cells). the following scenarios are examined: 256, 512, and 1024 bidirectional tdm channels. the memory clock memclk is tied to the input mclk, which also clocks all internal processes, and also controls cpu access speed. a tm t ransmit pr ocess band width a. access to tx circular buffer control structure. one word read access is required per tdm channel every 4 frames. thus, one double-word access can retrieve 2 tdm channels every 4 frames (500 m s): (1 double-word read access / (2 channels * 500 m s)) * n tdm channels = 1000 * n accesses/s. ? 256 tdm channels 0.256 m accesses / s ? 512 tdm channels 0.512 m accesses / s ? 1024 tdm channels 1.024 m accesses / s b. access to the transmit circular buffers. one double word (32-bit) write access is required to transfer a tdm channel into a circular buffer every four frames (500 m s). as well, four additional read accesses are required to retrieve the data byte by byte: ((1 double-word write access + 4 half-word read accesses) / 500 m s) * n tdm channels = 10000 * n accesses/s. ? 256 tdm channels 2.56 m accesses / s ? 512 tdm channels 5.12 m accesses / s ? 1024 tdm channels 10.24 m accesses / s c. access to transmit event schedulers. assuming that we have selected 16 vc pointers (one word each) per frame, we require eight double-word read accesses per scheduler per frame (125 m s): (8 double-word read accesses / 125 m s) * n event schedulers = 64000 * n accesses/s. ? 1 scheduler 0.064 m accesses / s ? 3 schedulers 0.192 m accesses / s d. transmit control structure accesses. each cell transmitted requires three control double-word read accesses (for the twelve bytes of control data at the start of each transmit control structure), one control double-word write access (to update the current entry, sequence number, and circular buffer pointer ?elds of the transmit control structure), as well as up to 24 double-word read accesses (to select up to 48 tdm circular buffer addresses per cell) to know which data to transfer, for a total of up to 28 memory accesses per cell transmitted. 256 tdm channels represent a rate of ~ 5.5 cells / 125 m s; 512 tdm channels represent a rate of ~11 cells / 125 m s; etc. (28 double-word memory accesses * estimated cell arrival rate (per 125 m s) = 224000 * cell arrival rate. * the case of one tdm channel per cell has been optimized to outperform the standards stated herein. the case of vcs having odd numbers of tdm channels is slightly worse than the number given. ? 256 tdm channels 1.232 m accesses / s ? 512 tdm channels 2.464 m accesses / s ? 1024 tdm channels 4.928 m accesses / s sub-total external memory access bandwidth requirements to support the tdm to atm transmit process: minimum requirements: ~ 4.11 m accesses / sec maximum requirements: ~ 16.4 m accesses / sec
mt90500 152 a tm receive pr ocess band width a. access to vc look-up table. assuming an overall inbound traf?c rate of 25.6 mbps, the external memory to internal tdm memory structure encounters a maximum of ~60,000 cells per second (i.e. (3.2 mbytes/s) / (53 bytes/cell) = 60377.36 cells / s). assuming an overall inbound traf?c of 155.52 mbps (again, 1m = 1 000 000), the external memory to internal tdm memory structure encounters ~400,000 cells per second (i.e. (19.44 mbytes/s) / (53 bytes/cell) = 366792.45 cells / s). there is one double-word read access per cell. ? 25.6 mbps ~ 0.06 m accesses / s ? 155.52 mbps ~ 0.4 m accesses / s b. rx_sar control structure accesses. each received cell requires three control double-word read accesses (for the twelve bytes of control data at the start of each rx_sar control structure), one control double-word write access (to update the current entry and tdm write pointer ?elds of the rx_sar control structure), as well as up to 24 double-word read accesses (to select up to 48 rx circular buffer base addresses per cell) to know which data to transfer, for a total of up to 28 memory accesses per cell transmitted. 256 tdm channels represent a rate of ~ 5.5 cells / 125 m s; 512 tdm channels represent a rate of ~11 cells / 125 m s; etc. 28 double-word read accesses * estimated cell arrival rate (per 125 m s) = 224000 * cell arrival rate. ? 256 tdm channels 1.232 m accesses / s ? 512 tdm channels 2.464 m accesses / s ? 1024 tdm channels 4.928 m accesses / s c. access to the receive circular buffers. one double-word (32-bit) read access followed by a double-word write access (to clear the underrun bit after the byte has been read) per tdm channel every four frames (500 m s). four times as many accesses are required to transfer the data from the received cell to the circular buffer, byte per byte. ((1 double-word read access + 1 double-word write access + 4 half-word write accesses) / 500 m s * n tdm channels = 12000 * n accesses/s. ? 256 tdm channels 3.07 m accesses / s (5.63 m accesses / s) ? 512 tdm channels 6.14 m accesses / s (11.3 m accesses / s) ? 1024 tdm channels 12. 3 m accesses / s (22.5 m accesses / s) d. access to the external memory to internal tdm memory structure. one double-word read access is required per tdm channel every 4 frames (500 m s): (1 double-word read access / 500 m s) * n tdm channels = 2000 * n accesses/s. ? 256 tdm channels 0.512 m accesses / s ? 512 tdm channels 1.024 m accesses / s ? 1024 tdm channels 2.048 m accesses / s sub-total of external memory access bandwidth requirements to support the atm to tdm receive process: minimum requirements: ~ 7.76 m accesses / s maximum requirements: ~ 29.9 m accesses /s t otal band width requirements total of external memory access bandwidth requirements to support both the tdm to atm transmit and the atm to tdm receive process: minimum requirements: ~ 11.9 m accesses / s maximum requirements: ~ 46.3 m accesses /s
mt90500 153 the above maximum requirement de?nes the theoretical minimum clock frequency the design must achieve to support 1024 x 64 kbps bidirectional channels with 1024 vcs. assuming a 29% margin for cpu accesses, aal0 cell processing, and random lost memory access ef?ciency, the mt90500 should be supplied with a master clock (mclk) of 60 mhz to support 1024 x 64 kbps bidirectional channels with 1024 vcs. it is also recommended to select ssram to minimize turnaround cycles, for the greatest memory ef?ciency. 7.5 cbr throughput delay delay through the mt90500, from tdm bus to tdm bus, depends on a number of variables, not all of which are under the control of the designer. the following discussion omits atm network delay (transmission delay), tdm switching delay (caused by moving a tdm channel from time slot 0 to time slot 32, for instance) and cdv buffer delay (avg. lead of the rx circular buffer). an example of large delay would use aal1, n=1, fully-?lled cells, the delay for which can be typically 66 frames (8.25 msec). this is due to the following factors: 4 frames tx tdm input frame buffer 3 frames average tx offset (tdm write pointer to tx_sar read pointer) 47 frames cell assembly (47 byte payload) 8 frames rx circular buffer delay (avg. lead = 02h, = 8 frames) 4 frames rx tdm output frame buffer. ---- 66 frames minimum delay is achieved using larger trunking numbers (n > 47) or using partially ?lled cells with n = partial- ?ll- level. delay in this case will be 3 msec to 5 msec, with cdv buffers set to the minimum. to these numbers, the designer may wish to add the application-speci?c delays: atm network transmission delay, atm switching delay, cdv buffer delay, and tdm switching delay.
mt90500 154 7.6 other applications 7.6.1 payload switching figure 71 indicates how the mt90500 can be used as a payload switch. in such an application, tdm data received in the cell payload of one atm vc can be transmitted from the mt90500 as the cell payload of a different atm vc. note that this constrains the receive circular buffers to 64 bytes (the same size as the transmit circular buffer), which limits the cdv tolerance. a major consideration in this application is delay tolerance of the transported channels, as the reassembly delay and segmentation delay of this payload switch are added to the end points/ reassembly delay and segmentation delay. 7.6.2 tdm switching and loopback figure 72 indicates how the mt90500 can be used to switch one or more tdm channels. in such an application, tdm data input on a speci?c time slot and stream can be output from the mt90500 on a different tdm time slot and stream. (when an input tdm channel from a speci?c trunk is output back to that trunk, this switching can be termed a loopback.) note that for this application the receive circular buffers for the tdm channels involved must be 64 bytes (the same size as the transmit circular buffer). to perform loopback or switching of a speci?c tdm input channel to a speci?c tdm output channel, the transmit circular buffer control structure is ?rst programmed to have the desired input tdm channel written to a particular tx circular buffer. the external memory to internal memory control structure is then programmed to set up an rx circular buffer 64 bytes long, at the same address as the tx circular buffer just enabled. at the same time, the desired output tdm channel is set up to read from this rx circular buffer (shared buffer). no further cpu involvement is required. figure 71 - tdm payload switching rx sar tx sar circular buffer arriving atm cells transmitted atm cells ( 64 bytes) n arriving vcs, m transmitted vcs, k tdm channels k tdm channels circular buffer (64 bytes) circular buffer (64 bytes) k circular buffers (serve as receive and transmit)
mt90500 155 the input channel is now automatically written to the shared buffer, and the output channel is automatically read from the shared buffer, resulting in the input channel being written to the output channel. the throughput delay in this setup is 1 msec. this is due to the 4-frame tdm input frame buffer followed by the 4-frame tdm output frame buffer. 7.6.3 ds0 trunking, or dynamic tdm channel re-mapping the mt90500 can be used in trunking applications. in trunking applications it is often desirable to maintain an atm vc of constant bandwidth (constant nx64) but to re-map the tdm channels within the atm vc to different tdm channels on the backplane or tdm trunks. given an established vc, and the need to shut down a tdm channel and re-use the bandwidth within the vc, re-mapping a tdm channel can be done on the mt90500 as follows: 1) tristate the output tdm channel at the reassembly device (receive tdm end), using the oe registers, to end the old tdm channel connection. 2) re-write the tdm-channel-to-tx-circular-buffer mapping in the transmit circular buffer control structure at the segmentation device (transmit end). this is done by writing a new time slot and/or stream into the word-entry associated with the particular tx circular buffer. 3) re-write the rx-circular-buffer-to-tdm-channel mapping in the external memory to internal memory control structure at the reassembly device (receive tdm end). this is done by writing a new tdm channel # into the ?rst word of the two-word-entry associated with the particular rx circular buffer. 4) turn on the output tdm channel at the reassembly device (receive tdm end), using the oe registers, to start the new connection. figure 72 - tdm-to-tdm loopback/switching circular buffer input tdm channels output tdm channels ( 64 bytes) circular buffer (64 bytes) circular buffer (64 bytes) circular buffers (receive and transmit programmed into same addresses) tdm input frame buffer tdm output frame buffer
mt90500 156 7.6.4 scsa message channel figure 73 shows how the corsig/mc pins are used in an scsa message channel application. figure 73 - scsa message bus application typical message bus controller + 5 v mc mc ct bus or scbus mctx mcrx mcclk txda rxda dclk clkx2 mt90500 cxda
package outlines metric quad flat pack - l suf?x note: governing controlling dimensions in parenthesis ( ) are in millimeters. dim 44-pin 64-pin 100-pin 128-pin min max min max min max min max a - 0.096 (2.45) - 0.134 (3.40) - 0.134 (3.40) - 0.154 (3.85) a1 0.01 (0.25) - 0.01 (0.25) - 0.01 (0.25) - 0.00 0.01 (0.25) a2 0.077 (1.95) 0.083 (2.10) 0.1 (2.55) 0.12 (3.05) 0.1 (2.55) 0.12 (3.05) 0.125 (3.17) 0.144 (3.60) b 0.01 (0.30) 0.018 (0.45) 0.013 (0.35) 0.02 (0.50) 0.009 (0.22) 0.015 (0.38) 0.019 (0.30) 0.018 (0.45) d 0.547 bsc (13.90 bsc) 0.941 bsc (23.90 bsc) 0.941 bsc (23.90 bsc) 1.23 bsc (31.2 bsc) d 1 0.394 bsc (10.00 bsc) 0.787 bsc (20.00 bsc) 0.787 bsc (20.00 bsc) 1.102 bsc (28.00 bsc) e 0.547 bsc (13.90 bsc) 0.705 bsc (17.90 bsc) 0.705 bsc (17.90 bsc) 1.23 bsc (31.2 bsc) e 1 0.394 bsc (10.00 bsc) 0.551 bsc (14.00 bsc) 0.551 bsc (14.00 bsc) 1.102 bsc (28.00 bsc) e 0.031 bsc (0.80 bsc) 0.039 bsc (1.0 bsc) 0.256 bsc (0.65 bsc) 0.031 bsc (0.80 bsc) l 0.029 (0.73) 0.04 (1.03) 0.029 (0.73) 0.04 (1.03) 0.029 (0.73) 0.04 (1.03) 0.029 (0.73) 0.04 (1.03) l1 0.077 ref (1.95 ref) 0.077 ref (1.95 ref) 0.077 ref (1.95 ref) 0.063 ref (1.60 ref) a 1 a index d 1 b e e 1 e pin 1 d a 2 notes: 1) not to scale 2) top dimensions in inches warning: this package diagram does not apply to the mt90810ak 100 pin package. please refer to the data sheet for exact dimensions. l l1 3) the governing controlling dimensions are in millimeters for design purposes ( )
package outlines note: governing controlling dimensions in parenthesis ( ) are in millimeters. dim 160-pin 208-pin 240-pin min max min max min max a - 0.154 (3.92) .161 (4.10) - 0.161 (4.10) a1 0.01 (0.25) 0.01 (0.25) 0.02 (0.50) 0.01 (0.25) 0.02 (0.50) a2 0.125 (3.17) 0.144 (3.67) .126 (3.20) .142 (3.60) 0.126 (3.2) 0.142 (3.60) b 0.009 (0.22) 0.015 (0.38) .007 (0.17) .011 (0.27) 0.007 (0.17) 0.010 (0.27) d 1.23 bsc (31.2 bsc) 1.204 (30.6) 1.360 bsc (34.6 bsc) d 1 1.102 bsc (28.00 bsc) 1.102 (28.00) 1.26 bsc (32.00 bsc) e 1.23 bsc (31.2 bsc) 1.204 bsc (30.6 bsc) 1.360 bsc (34.6 bsc) e 1 1.102 bsc (28.00 bsc) 1.102 bsc (28.00 bsc) 1.26 bsc (32.00 bsc) e 0.025 bsc (0.65 bsc) 0.020 bsc (0.50 bsc) 0.0197 bsc (0.50 bsc) l 0.029 (0.73) 0.04 (1.03) 0.018 (0.45) 0.029 (0.75) 0.018 (0.45) 0.029 (0.75) l1 0.063 ref (1.60 ref) 0.051 ref (1.30 ref) 0.051 ref (1.30 ref)
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